Semiconductor Memory Array Bank Segmentation for Disturb Reduction
Solution Overview
Problem
Existing nonvolatile memory modules face challenges in reducing the number of memory gate drivers while minimizing data corruption due to disturb occurrences during writing in small byte units, leading to increased chip area and reliability issues.
Innovation Solution
The implementation of a semiconductor integrated circuit device with a memory array configuration that includes sub-arrays, common write gate line driving circuits, power supply line driving circuits, and read gate line transfer circuits, along with a data line selecting circuit and amplifier circuit, reduces the number of memory gate drivers and decreases disturb occurrences without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of memory cells coupled to one memory gate line is limited to reduce disturb occurrences, then reliability is improved, but the number of memory gate drivers increases and chip area increases
Solution Approach 1:
The memory array is divided into multiple banks, where each bank contains a subset of memory cells coupled to a memory gate line. This segmentation allows the system to limit the number of memory cells per gate line while maintaining overall memory capacity, thereby reducing disturb occurrences without proportionally increasing the number of gate drivers.
Solution Approach 2:
The patent introduces a bank selection mechanism that adds a dimensional layer to memory addressing. Instead of simply increasing the number of gate lines, the system uses bank selection signals to divide the memory space, effectively reducing the load per gate line while maintaining scalability without linearly increasing driver count.
2Reliability
If the number of memory cells coupled to one memory gate line is limited to reduce disturb occurrences, then reliability is improved, but chip area increases
Solution Approach 1:
By segmenting the memory array into banks with fewer memory cells per gate line, the patent reduces disturb-related threshold voltage variations. This segmentation is achieved through efficient spatial arrangement that maintains compact chip area while limiting the number of cells exposed to simultaneous write operations on a single gate line.
Solution Approach 2:
Multiple banks are combined under a unified control structure that shares gate drivers and control logic. This merging approach allows the system to achieve the reliability benefits of limited cells per gate line while consolidating driver resources, thereby avoiding proportional increases in chip area.
3Adaptability or versatility
If writing in small byte units is implemented, then adaptability is improved, but disturb occurrences increase leading to data corruption
Solution Approach 1:
The memory array is segmented into banks that can be independently selected and accessed. This segmentation enables small byte-unit writes by allowing selective activation of specific banks containing only the necessary memory cells, thereby limiting disturb occurrences to relevant regions while maintaining writing flexibility.
Solution Approach 2:
The patent implements local quality by enabling selective bank activation based on write address patterns. When a small byte write is performed, only the specific bank containing the target cells is activated, while other banks remain inactive. This localized access pattern maintains adaptability for small writes while confining disturb effects to minimal regions.
Data Source
AI summary
This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.