Memory Array Biasing Circuit for Temperature Compensation
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Solution Overview
Problem
Memory systems, particularly those used for in-memory computation, are temperature-sensitive, leading to variations in speed, precision, and power consumption due to changes in channel currents of CMOS transistors, which can be inefficiently compensated for using output circuitries like sense amplifiers and ADCs, resulting in bulky and high-power systems.
Innovation Solution
A memory system with a temperature-dependent biasing circuit that adjusts the biasing voltage for memory cells based on temperature, either by reducing voltage at higher temperatures or increasing it at lower temperatures, to maintain consistent performance across different operating temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If output circuitries like sense amplifiers and ADCs are used to compensate temperature effects, then temperature sensitivity is reduced, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the temperature compensation function from the output circuitry and relocates it to the memory cell level by modifying the cross-coupled inverter structure. This allows temperature effects to be compensated locally at each memory cell without requiring complex output circuitries like sense amplifiers and ADCs, thereby reducing overall device complexity while maintaining temperature stability
Solution Approach 2:
The patent introduces an intermediate element (the modified cross-coupled inverter with temperature-compensating feedback) that acts as a mediator between the memory cell and the output circuitry. This intermediate structure provides temperature compensation at the cell level, eliminating the need for complex temperature compensation circuitries at the output stage
2Reliability
If output circuitries like sense amplifiers and ADCs are used to compensate temperature effects, then temperature sensitivity is reduced, but power consumption increases
Solution Approach 1:
The patent removes the power-intensive output circuitries (sense amplifiers and ADCs) from the temperature compensation path and replaces them with a low-power cross-coupled inverter-based compensation mechanism integrated at the memory cell level, significantly reducing power consumption while maintaining temperature compensation effectiveness
Solution Approach 2:
The modified memory cell structure provides its own temperature compensation through the cross-coupled inverter feedback mechanism, eliminating the need for external power-intensive compensation circuitries. The cell self-regulates its temperature effects through the inherent properties of the cross-coupled inverter configuration
3Use of energy by moving object
If memory cells operate in subthreshold regime to reduce power, then power consumption decreases, but temperature sensitivity increases
Solution Approach 1:
The patent modifies the operating parameters of the memory cell by implementing a cross-coupled inverter feedback mechanism that dynamically adjusts the effective threshold voltage and operating point of the transistors. This parameter adjustment allows the cell to maintain stable operation across temperature variations while operating in the low-power subthreshold regime, effectively decoupling power consumption from temperature sensitivity
Data Source
AI summary
A memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, where the memory cells are organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.