Self-Correcting Memory Array Using Triple-Copy Bit Comparison
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Solution Overview
Problem
Existing memory arrays face challenges in efficiently detecting and correcting localized data corruption, such as radiation-induced errors, which can lead to unpredictable results and require additional parity bits or complex error-correcting codes.
Innovation Solution
A self-correcting memory device (SCMD) with a non-destructive memory array and NOR gates compares data across multiple rows, providing per-bit change indications to fetch and write correct values from a third copy, ensuring data integrity without additional error correction bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error-correcting codes (ECC) are used to detect and correct errors, then data integrity is improved, but device complexity and resource overhead increase
Solution Approach 1:
The patent stores multiple copies of data in the memory array and uses these copies for error detection and correction. Instead of adding complex ECC bits, the system creates redundant copies of the actual data and compares them to identify and correct errors, thereby maintaining data integrity without increasing device complexity through traditional error correction codes
Solution Approach 2:
The memory system performs self-diagnosis and self-correction by comparing multiple copies of stored data. The system automatically detects discrepancies between copies and corrects errors without requiring external error correction logic, enabling the memory to service its own error correction needs and reducing overall device complexity
2Reliability
If additional parity bits are added for error detection, then error detection capability is improved, but storage capacity and manufacturing precision requirements worsen
Solution Approach 1:
Instead of adding parity bits that require precise voltage control for reliable detection, the patent uses multiple copies of the actual data stored in the memory array. This approach provides error detection capability without the need for additional parity bits and their associated voltage control precision requirements
Solution Approach 2:
The patent extracts the error detection function from the traditional parity bit mechanism and implements it through data copying and comparison. By removing the need for parity bits and their complex voltage control requirements, the system achieves error detection while reducing manufacturing precision demands
3Productivity
If multiple rows are activated for comparison, then error detection speed is improved, but energy consumption increases
Solution Approach 1:
The patent merges the error detection function with the normal memory read operation. By activating multiple rows simultaneously and comparing their contents during what would otherwise be a standard memory access, the system achieves fast error detection without requiring separate dedicated error detection cycles that would consume additional energy
Data Source
AI summary
A self-correcting memory device (SCMD) includes a non-destructive memory array that includes memory cells arranged in rows and columns that includes a storage section, a comparison section, a comparing element, a selective write unit and a row decoder. The storage section stores a first copy, a second copy and a third copy of a data item in physically separated columns. The comparison section temporarily stores the first copy in a first row and the second copy in a second row. The comparing element compares between bits of the first and second rows and provides at least one per bit change indication. The selective write unit receives at least one per bit change indication and fetches from the third copy a correct value for each bit having a positive bit change indication. The row decoder concurrently writes each correct value back to its bit location in the first and second copies.