Memory Array Bit-Line Conversion for Linear Low-Power IMC

The patent replaces the traditional mechanical/electronic analog-to-digital converter with a neural network-based computational system. The neural network processes analog signals from the memory array directly through software algorithms, eliminating the need for hardware ADC circuits. This substitution achieves linear converting characteristics through controlled incremental operations while significantly reducing power consumption by performing computations in the digital domain rather than requiring energy-intensive analog circuitry.

The patent segments the analog-to-digital conversion process into multiple incremental steps, where the analog signal is converted through a series of smaller voltage steps rather than a single large conversion. Each step involves comparing the analog voltage with a reference voltage and adjusting incrementally. This segmentation achieves high linearity by breaking down the non-linear conversion into linear incremental operations, while the energy consumption is distributed across multiple low-power comparison operations rather than requiring a high-power single-step converter.

The patent implements a universal computing platform where the memory array serves multiple functions: it acts as both the data storage medium and the computational element for analog-to-digital conversion. The same memory structure that stores data is used to perform the converting operation through controlled voltage adjustments and comparisons. This eliminates the need for separate, complex ADC circuitry, reducing device complexity while maintaining full converting functionality through the multi-functional memory array system.