Memory Arrays With Multi-Elevational Global Bitlines
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Solution Overview
Problem
Conventional cross-point memory arrays face challenges in tightly packing memory cells due to limitations in the arrangement and orientation of wordlines and bitlines, which restricts the miniaturization of memory units and efficiency in data storage and retrieval.
Innovation Solution
The proposed memory arrays utilize multiple elevational levels for global bitlines and optimize the placement of memory cell material and access devices between wordlines and vertical bitline pillars, reducing the planar area of each memory unit to achieve more compact and efficient packing, with options for contiguous or discontinuous access device placement to further minimize cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional cross-point memory arrays use traditional arrangement of wordlines and bitlines, then the structure is simple and easy to manufacture, but the memory cell packing density is low and planar area is large
Solution Approach 1:
The patent introduces multiple elevational levels for global bitlines, transitioning from a single-plane arrangement to a three-dimensional configuration. This allows bitlines to be positioned at different heights, enabling more compact packing of memory cells in the planar view while maintaining proper electrical connections through vertical structures.
Solution Approach 2:
The patent implements a hierarchical structure where vertical bitline pillars extend through multiple wordline layers, and global bitlines at different elevational levels are interconnected through these pillars. This nested arrangement allows efficient use of space by stacking functional elements vertically rather than spreading them out in a single plane.
2Quantity of substance
If memory cells are tightly packed to increase storage density, then storage capacity improves, but access device placement becomes more difficult and manufacturing precision requirements increase
Solution Approach 1:
By positioning access devices and memory cell material at different elevational levels and using vertical bitline pillars as connection structures, the patent enables tighter horizontal packing of memory cells while maintaining adequate spacing and alignment tolerances through the vertical dimension.
Solution Approach 2:
The patent divides the bitline structure into vertical pillars that extend through multiple wordline layers, with global bitlines positioned at different elevational levels. This segmentation allows independent optimization of horizontal packing density and vertical connection alignment, reducing the interdependence of manufacturing precision requirements.
Data Source
AI summary
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.