3D Memory Array Wall Structure to Prevent Block-Bending
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Solution Overview
Problem
The technical challenge lies in preventing 'block-bending' during the fabrication of memory arrays, where vertically-stacked memory cells can tilt or bend sideways, leading to structural instability and potential defects in the memory array formation.
Innovation Solution
The method involves forming a memory array with laterally-spaced memory blocks comprising a vertical stack of alternating insulative and conductive tiers, where operative channel-material strings extend through these tiers, and the insulative and conductive tiers in the stair-step region form operative stair-step structures with specifically oriented and spaced elevationally-extending walls, ensuring structural integrity and preventing block-bending.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are formed in a memory array, then memory density is improved, but structural stability deteriorates due to block-bending
Solution Approach 1:
The memory array is divided into multiple memory blocks with individually formed vertically-stacked memory cells. Each memory block is independently structured with its own set of alternating insulative and conductive tiers, allowing localized structural support and preventing bending across the entire array. This segmentation enables high memory density while maintaining structural stability through distributed support structures.
Solution Approach 2:
The patent implements locally-optimized structural features including elevationally-extending walls positioned between memory blocks, stair-step structures at block edges, and selectively-formed conductive regions. These local structural enhancements provide targeted support to prevent block-bending in specific areas where vertically-stacked cells create stress concentrations, thereby maintaining overall structural stability while enabling high-density vertical stacking.
2Quantity of substance
If vertically-stacked memory cells are formed, then manufacturing complexity increases, but memory capacity is improved
Solution Approach 1:
The fabrication process is divided into modular stages where alternating insulative and conductive tiers are formed sequentially in discrete memory blocks. Each block can be independently processed and validated, reducing the overall manufacturing complexity despite the vertical stacking architecture. This segmented approach enables high memory capacity while managing fabrication complexity through standardized repeating units.
Solution Approach 2:
The patent employs preliminary formation of structural support elements including elevationally-extending walls and stair-step structures before completing the vertical stack formation. Channel openings and charge-trapping layers are also prepared in advance in specific regions. These preliminary actions simplify the subsequent fabrication steps and reduce the overall manufacturing complexity while enabling high-density vertical memory structures.
3Strength
If stair-step structures are formed with elevationally-extending walls, then structural integrity is improved, but device complexity increases
Solution Approach 1:
The stair-step structures feature asymmetric elevationally-extending walls positioned specifically at the edges and between memory blocks, rather than uniform structures throughout. This asymmetric configuration provides targeted structural reinforcement where block-bending stress is highest, improving structural integrity while adding minimal complexity compared to a fully symmetric design. The walls are strategically placed to maximize structural benefit with minimal additional components.
Data Source
AI summary
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.