3D Memory Array Isolation Structure for Post-Gate BSG Cuts
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Solution Overview
Problem
Existing semiconductor technologies face challenges in forming BSG cut structures between neighboring gate line slit structures during the replacement of sacrificial layers with gate layers, leading to potential failure in gate-last processes due to blocking by multiple BSG cut structures.
Innovation Solution
The formation of BSG cut structures is achieved through backside processing after the replacement of sacrificial layers with gate layers, allowing for the creation of separate sub-arrays within an array of vertical memory cell strings, using insulating materials to form trenches and recess the gate layers, ensuring effective separation and individual control of sub-arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If multiple BSG cut structures are formed between neighboring gate line slit structures during sacrificial layer replacement, then sub-arrays can be separated, but the gate-last process fails due to blocking by multiple BSG cut structures
Solution Approach 1:
The patent inverts the conventional sequence by forming BSG cut structures after gate layer deposition rather than during sacrificial layer replacement. This reversal eliminates the blocking issue while achieving sub-array separation, as the gate layers are already in place to define the memory cell structure before the BSG cuts are made.
Solution Approach 2:
The patent performs preliminary gate layer deposition and patterning before forming the BSG cut structures. This preliminary action ensures that the gate layers are properly established to define memory cells, and subsequent BSG cuts can be made without interfering with gate layer formation, thus preventing process failure.
2Weight of moving object
If BSG cut structures are formed during sacrificial layer replacement, then sub-arrays can be separated, but control over threshold voltages and memory cell operations is compromised
Solution Approach 1:
By inverting the formation sequence to create BSG cut structures after gate layers are deposited, the patent enables independent electrical control of each sub-array. The gate layers remain intact during separation, allowing precise control over threshold voltages and memory cell operations in each sub-array without interference from the cutting process.
3Weight of moving object
If multiple BSG cut structures are formed early in the process, then sub-arrays are separated, but over-erase conditions occur and electronic properties deteriorate
Solution Approach 1:
The patent performs preliminary gate layer formation and patterning before creating BSG cut structures. This preliminary action establishes proper electrical isolation and control mechanisms that prevent over-erase conditions. The gate layers are already in place to define memory cell regions, so subsequent BSG cuts do not cause harmful electronic property degradation.
Data Source
AI summary
Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.