Memory Array Cache Redundancy Mapping Defective Cells
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Solution Overview
Problem
Memory systems with cache redundancy face challenges due to defective cells in both the main array and cache memory, which can disrupt data flow and render rows or columns unusable, necessitating improved redundancy logic for correct data routing.
Innovation Solution
An integrated circuit design incorporating a primary array and a redundant array, along with a cache replacement store, maps defective locations in the array cache to the redundant array, using the cache replacement store to ensure data integrity and reliability by routing data through the redundant array when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy logic is added to handle defective cells in the main array, then reliability is improved, but device complexity increases due to additional routing requirements for cached data
Solution Approach 1:
The patent merges the redundancy functions for the main array and cache array into a single integrated replacement array. This consolidation allows a single redundancy structure to serve dual purposes: replacing defective cells in the main array and replacing defective cells in the cache array, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The replacement array is designed with multi-functionality to handle defective locations in both the main array and the cache array. The same replacement array serves universal redundancy needs across different array levels, reducing the overall redundancy overhead that would otherwise require separate dedicated redundancy structures for each array
2Reliability
If a replacement array is used for defective cells in the main array, then reliability is improved, but data transfer complexity increases due to additional routing requirements
Solution Approach 1:
The cache array serves as an intermediary structure that facilitates data transfer between the main array and the replacement array. When defective cells are detected, the cache array enables proper routing of cached data to the replacement array, simplifying the data transfer process compared to direct complex routing paths
3Device complexity
If defective cells in the cache array are not addressed, then device complexity is reduced, but reliability deteriorates as defective cells can render entire rows or columns unusable
Solution Approach 1:
The system performs preliminary identification and mapping of defective locations in the cache array during initialization. Defective cache locations are pre-mapped to corresponding locations in the replacement array, enabling automatic redirection of data operations before they cause reliability issues during normal operation
Data Source
AI summary
An integrated circuit including a memory, an array cache, and a cache replacement store is described. The memory includes a primary array and a redundant array. The integrated circuit also includes circuitry configured to transfer data into or out of the primary array using the array cache. For defective locations in the array cache, the circuitry is configured to use the cache replacement store in the transfer of data in place of the defective locations in the array cache, and map addresses in the primary array corresponding to the defective locations in the cache array to the redundant array.