3D Memory Array Layout for Isolated Vertical Cell Strings
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Solution Overview
Problem
Current methods for forming memory arrays, such as NAND architecture, face challenges in efficiently creating vertically-stacked memory cells with precise control over gate formation and electrical connectivity, leading to potential shorting and operational issues.
Innovation Solution
The method involves forming a stack with vertically-alternating conductive and insulative tiers, using sacrificial materials and etching techniques to create channel-material strings and trenches, and forming conductive lines that directly couple with the conductor tier, while ensuring lateral electrical isolation between memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form vertically-stacked memory cells, then memory array structure is achieved, but electrical connectivity control is imprecise leading to shorting risks
Solution Approach 1:
The patent applies preliminary action by forming sacrificial material structures (mandrels) before forming the actual memory cell structures. These sacrificial mandrels are positioned at specific locations where memory cells will eventually be formed, allowing precise control over where conductive materials will be deposited and where electrical connections will be established, thereby preventing shorting between adjacent memory blocks.
Solution Approach 2:
The patent uses sacrificial material as an intermediary element that temporarily occupies space and guides the formation of electrical connections. These sacrificial structures mediate between the deposition process and the final memory cell structure, ensuring that conductive materials are deposited only in desired locations and that proper electrical isolation is maintained between adjacent memory blocks.
2Productivity
If vertically-stacked memory cells are formed with dense packing, then memory density is improved, but gate formation control becomes more difficult
Solution Approach 1:
The patent segments the formation process into distinct stages using sacrificial material for each memory block region. By dividing the array into separately-controlled regions with individual sacrificial mandrels, the process allows high-density packing while maintaining independent control over gate formation in each segment, making the overall manufacturing process more manageable despite the high density.
Solution Approach 2:
The sacrificial material is deposited and patterned in advance to define the precise locations and dimensions of future memory cell gates. This preliminary structuring enables subsequent high-density vertical stacking while the gate formation process itself remains controlled and manageable, as the sacrificial structures serve as templates that guide material deposition and etching processes.
3Reliability
If sacrificial material is removed completely from trenches, then electrical isolation is improved, but structural support is reduced
Solution Approach 1:
The patent extracts (removes) the sacrificial material from the trenches after the memory cell structures have been formed around it. At this stage, the memory cell structures themselves provide the necessary structural support, so removing the sacrificial material achieves complete electrical isolation between adjacent memory blocks without compromising structural integrity. The extracted sacrificial material had served its purpose as a temporary guide and isolator.
Solution Approach 2:
The structural support function is transferred to the memory cell structures themselves before the sacrificial material is removed. The memory cell structures are formed around the sacrificial material in advance, and once they are in place, they assume the structural support role, allowing the sacrificial material to be completely removed for electrical isolation without creating structural weaknesses.
Data Source
AI summary
Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.