Memory Array Channel Bias Control for Adjacent Cell Disturbance
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Solution Overview
Problem
As critical dimensions of memory cells in integrated circuits shrink, adjacent memory cells experience significant disturbance, leading to instability in programming states due to shared gate structures, particularly in NAND flash memory arrays.
Innovation Solution
A method for operating a memory array where memory cells are programmed or inhibited by applying distinct biases to their channels, with one memory cell having a higher channel bias to stabilize the program-inhibited state, thereby reducing interference between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size and pitch are reduced to increase storage capacity, then storage capacity per unit area is improved, but disturbance between adjacent memory cells increases
Solution Approach 1:
The patent applies different bias voltages to different memory cells based on their programming state requirements. Specifically, a first bias voltage is applied to a first memory cell to be programmed, a second bias voltage is applied to a second memory cell to inhibit programming, and a third bias voltage is applied to a third memory cell adjacent to the second cell. This local differentiation of electrical conditions allows the system to maintain stable programming states while operating at reduced cell dimensions where disturbance effects are more pronounced.
2Device complexity
If a single bias voltage is applied to all memory cells, then device complexity is reduced, but programming state stability deteriorates due to disturbance from adjacent cells
Solution Approach 1:
The patent changes the electrical parameter (bias voltage) applied to different memory cells depending on their programming state. By applying a first bias voltage to cells being programmed, a second bias voltage to cells that should remain unprogrammed, and a third bias voltage to adjacent cells, the system dynamically adjusts electrical conditions to maintain stability. This parameter differentiation resolves the contradiction by allowing complex control only where necessary to prevent disturbance, while simpler single-bias operation can be used where disturbance is not an issue.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability of program-inhibited states by boosting the channel potential of memory cells, improving the overall characteristics of the memory array by maintaining the stability of programmed and inhibited states.
Implementation Method 1
A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programing of the second memory cell.
Data Source
AI summary
A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programing of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programing of the third memory cell. The first bias and the third bias are different.