3D Memory Array Channel Etching for Uniform Opening Spacing
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Solution Overview
Problem
Current methods for forming memory arrays comprising strings of memory cells face challenges in achieving efficient and uniform patterning of channel openings and dummy openings, which affect the performance and reliability of the memory cells.
Innovation Solution
The method involves forming a construction with vertically-alternating insulative and wordline tiers, where channel openings and dummy openings are etched into the insulative and wordline tiers using the uppermost portion of the material as a mask, with channel openings being etched deeper than dummy openings, and channel material is formed within these openings to create operative and dummy channel-material strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel openings and dummy openings are etched using conventional patterning methods, then the memory array can be formed, but the uniformity and precision of opening spacing is insufficient
Solution Approach 1:
The patent segments the opening formation process into two distinct stages: first forming dummy openings at a relaxed pitch, then forming channel openings at the target pitch. This segmentation allows each stage to be optimized independently, achieving high precision without excessive overall process complexity
Solution Approach 2:
The patent performs preliminary action by first forming the dummy openings and their associated dummy channel material strings before forming the actual channel openings. This preliminary structure serves as a template that guides subsequent precise patterning operations, ensuring uniform spacing is achieved
2Reliability
If channel openings are etched deeper than dummy openings, then proper electrical coupling is achieved, but the etching process complexity increases
Solution Approach 1:
The patent applies local quality by creating different etch depths for different regions: channel openings are etched deeper to achieve proper electrical coupling, while dummy openings are etched shallower. This is accomplished through selective masking and staged etching processes that treat different locations differently, ensuring each region receives the appropriate treatment for its function
Solution Approach 2:
The patent uses dummy channel material strings as intermediaries that facilitate the differential etching process. These dummy strings serve as placeholders and masks that enable the channel openings to be etched to different depths than dummy openings, achieving proper electrical coupling without requiring complex direct control of the etching process
3Productivity
If vertically-stacked memory cells are formed with control circuitry below, then three-dimensional integration is achieved, but the fabrication process complexity increases
Solution Approach 1:
The patent implements vertical stacking of memory cells in the third dimension, allowing high-density integration without proportionally increasing lateral footprint. The control circuitry is positioned below the stacked memory cells, utilizing the vertical dimension for circuit integration. This dimensional transition enables higher productivity and integration density while managing fabrication complexity through standardized vertical processing techniques
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.