High Density Non-Volatile Memory Array Circuit Design
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Solution Overview
Problem
High-density non-volatile memory arrays face challenges with increasing resistance in active/diffusion reference lines, leading to voltage drops and reduced read operation margins, which are exacerbated by decreasing supply voltages, making read operations more critical and prone to failures.
Innovation Solution
The solution involves a memory array circuit with word lines and bit-lines where the gates of memory cell transistors are connected to different word lines, and the drains and sources are connected only to bit-lines, eliminating the need for separate reference lines, thereby reducing active/diffusion resistances and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If active/diffusion reference lines are used to connect selection transistors, then the memory array can perform read operations, but the resistance of reference lines increases significantly as transistor dimensions decrease, causing voltage drop and reduced read margins
Solution Approach 1:
The patent removes the reference line component entirely from the memory cell structure. By connecting bit-lines directly to drains and sources of memory cell transistors without intermediate reference lines, the invention extracts the problematic element causing voltage drop and eliminates the associated reliability issue.
Solution Approach 2:
The patent merges the functions of reference lines and bit-lines into a single structure. The bit-line serves dual purposes: as a data transmission line and as a reference potential line, eliminating the need for separate reference lines and reducing overall resistance in the signal path.
2Ease of operation
If separate reference lines are implemented in the memory array, then read operations can be performed, but the area of the memory array increases due to additional lines and connection structures
Solution Approach 1:
The bit-line is designed to perform multiple functions simultaneously: data transmission and reference potential provision. This multi-functionality eliminates the need for dedicated reference lines, reducing the total number of interconnect lines and minimizing memory array area occupation.
Solution Approach 2:
The invention extracts and removes the separate reference line structure from the memory array design. By eliminating this redundant component and its associated connection structures, the patent significantly reduces the area required for the memory array while maintaining full read operation capability.
3Productivity
If transistor dimensions are decreased to increase memory density, then more memory cells can be packed into the same area, but the resistance of active/diffusion lines increases, making read operations more critical and prone to failures
Solution Approach 1:
The patent removes the vulnerable reference line structures that are particularly susceptible to resistance increases at small dimensions. By eliminating these lines and using direct bit-line connections, the invention maintains read operation reliability even as transistor dimensions decrease and memory density increases.
Solution Approach 2:
The patent segments the memory cell structure to connect drains and sources directly to bit-lines without intermediate reference line segments. This segmentation eliminates the cumulative resistance effect that occurs in longer reference line paths, maintaining signal integrity at high memory density.
Data Source
AI summary
A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines.