Memory Array Circuit with Two-Bit Cells and Dynamic Sub-Bit Line Switching
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Solution Overview
Problem
Conventional memory array circuits are not designed to handle two-bit memory cells efficiently, as they require fixed connections for select lines and sub-bit lines, which limits their ability to store and read two bits of information at high speed due to significant parasitic capacitance and leakage current issues.
Innovation Solution
A memory array circuit with a grid of parallel word lines and sub-bit lines, where each memory cell has a pair of main electrodes connected to adjacent sub-bit lines, and switching elements controlled by signal lines to read two bits from different electrodes, reducing parasitic capacitance and enabling high-speed data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory array circuits use fixed connections for select lines and sub-bit lines, then the circuit structure is simple, but the ability to store and read two bits of information at high speed is limited due to significant parasitic capacitance and leakage current
Solution Approach 1:
The patent applies dynamics by making the connections between select lines and sub-bit lines configurable rather than fixed. Each memory cell can be dynamically connected to different sub-bit lines based on the read operation requirements, allowing the circuit to adapt its topology during operation. This dynamic reconfiguration enables optimized signal paths that minimize parasitic capacitance during high-speed read operations while maintaining structural simplicity through standardized connection patterns.
2Productivity
If conventional memory array circuits use fixed connections for select lines and sub-bit lines, then the circuit structure is simple, but leakage current issues prevent efficient two-bit storage and reading
Solution Approach 1:
The patent implements dynamics by enabling configurable connections between select lines and sub-bit lines through multiplexing structures. This allows the circuit to dynamically select optimal connection paths that minimize leakage current during read operations. By reconfiguring the signal paths based on the specific memory cells being read, the circuit can avoid fixed connection bottlenecks that cause leakage, thereby enabling efficient two-bit storage and reading at high speeds.
3Quantity of substance
If two-bit memory cells are used to increase storage density, then the quantity of information stored increases, but the operational speed decreases due to increased parasitic capacitance
Solution Approach 1:
The patent applies dynamics by implementing configurable connections that allow the memory array to reconfigure its topology during read operations. This enables the circuit to optimize signal paths specifically for high-speed read operations, separating the storage density benefit of two-bit cells from the speed penalty by allowing dynamic path selection that minimizes parasitic capacitance impact.
Solution Approach 2:
The patent applies segmentation by dividing the memory array into subblocks with independent multiplexer structures. Each subblock can be independently configured and read, allowing the system to manage parasitic capacitance effects locally rather than across the entire array. This segmentation enables optimized read paths for specific memory cells while isolating capacitance issues to smaller, more manageable sections.
Data Source
AI summary
A high-speed nonvolatile memory array has two-bit memory cells, each connected to a mutually adjacent pair of sub-bit lines. The sub-bit lines are connected to a common power supply line through switching elements controlled in a cyclic sequence by 2m signal lines, where m is an integer greater than one. The memory array circuit also has main bit lines, each connected to a group of m consecutive sub-bit lines through switching elements controlled in a cyclic sequence by m signal lines. Data are read through two mutually adjacent main bit lines from two memory cells selected so that the sub-bit lines connecting the two main bit lines to the two memory cells are located between the sub-bit lines connecting the two memory cells to the common power line, an arrangement that reduces parasitic capacitance.