Memory Array Row Clearing to Reduce Bus Occupancy
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Solution Overview
Problem
Existing memory devices require multiple external write commands to clear a portion of a memory array, which occupies the command/address and data bus for an extended period, consumes significant power, and prolongs the operation time.
Innovation Solution
Implementing a single row clear command that uses internally stored data patterns to clear memory cells, reducing the need for external data transmission and minimizing bus occupancy, power consumption, and operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple external write commands are used to clear memory cells, then the memory array can be cleared, but the command/address and data bus are occupied for an extended period
Solution Approach 1:
The patent stores data patterns internally in advance within the memory device. When a row clear command is received, the pre-stored patterns are immediately applied without requiring external data transmission, thus clearing the bus quickly while ensuring complete memory clearing
Solution Approach 2:
The patent combines multiple write operations into a single row clear command. Instead of transmitting separate write commands for each memory location, the internal circuitry generates and applies multiple data patterns in sequence through a single command interface, reducing bus occupancy to just the command transmission time
2Reliability
If multiple external write commands are used to clear memory cells, then the memory array can be cleared, but significant power is consumed
Solution Approach 1:
The memory device performs the clearing operation using its own internal resources. The internal circuitry generates the data patterns and controls the write operations autonomously after receiving a single row clear command, eliminating the need for continuous external data transmission and associated power consumption
Solution Approach 2:
By pre-storing data patterns internally, the device eliminates the need for repeated external data transmissions. The internal storage and generation of patterns reduces the active communication time and associated power consumption while ensuring complete clearing
3Reliability
If multiple external write commands are used to clear memory cells, then the memory array can be cleared, but the operation time is prolonged
Solution Approach 1:
The patent pre-stores multiple data patterns internally in advance. When clearing is needed, these patterns are immediately applied in sequence without waiting for external transmission, dramatically reducing the clearing operation time while ensuring all memory cells are properly cleared
Solution Approach 2:
The patent merges multiple sequential write operations into a single integrated row clear command execution. The internal circuitry handles the sequence of pattern applications autonomously, reducing the operation to just the command transmission time plus internal processing time, thereby significantly improving clearing speed
Data Source
AI summary
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.