Memory Array Clock Gating via Pre-Evaluated Enable Signals
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Solution Overview
Problem
Integrated circuits with embedded memory arrays face challenges in reducing power consumption without impacting system clock speed or access timing, as existing clock-gating techniques are limited by setup time requirements that not all memory enable signals can meet.
Innovation Solution
Generating clock gate enable signals at processing stages prior to the evaluation of memory enable signals to enable clock gating in input registers of the memory array, even when setup time requirements are not met, by using pre-evaluated conditional enable signals for early-stage circuitry like data and address input registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If clock-gating elements are inserted to reduce power consumption, then power consumption is reduced, but setup time requirements are not met for critical timing paths
Solution Approach 1:
The patent segments the clock gating approach by applying it selectively to non-critical timing paths (input registers) while excluding critical timing paths (memory enable signals) from clock gating. This allows power reduction in non-critical paths without compromising timing requirements of critical paths.
Solution Approach 2:
The patent applies different clock gating strategies to different parts of the timing paths. Input registers (non-critical) receive clock gating to save power, while memory enable signals (critical) maintain continuous clocking to ensure timing requirements are met. This local differentiation resolves the contradiction between power saving and timing reliability.
2Loss of energy
If clock-gating elements are inserted to reduce power consumption, then power consumption is reduced, but delay within the clock path increases
Solution Approach 1:
The patent segments clock gating application to only non-critical timing paths, leaving critical paths ungated. This ensures that the overall clock speed is maintained by avoiding delay in critical paths while still achieving power reduction through gating of non-critical paths.
Solution Approach 2:
Different quality of clock gating is applied locally: full gating for non-critical paths (input registers) to maximize power saving, and no gating for critical paths (memory enable signals) to maintain speed. This resolves the contradiction between power consumption and clock speed.
3Loss of energy
If memory enable signals are used for clock gating to reduce power consumption, then power consumption is reduced, but access timing is compromised
Solution Approach 1:
The patent segments the use of memory enable signals from clock gating. Instead of using memory enable signals as clock gate enable signals, the patent uses separate clock gate enable signals that are generated independently, allowing power reduction without affecting memory access timing.
Solution Approach 2:
The patent introduces intermediary clock gate enable signals that mediate between the system clock and the input registers. These intermediary signals allow timing adjustment and power reduction without directly using memory enable signals, thus preserving access timing integrity.
Data Source
AI summary
Dynamic power consumption is reduced by clock gating registers that synchronize memory input signals in an embedded memory array. Where a memory enable signal associated with a memory interface input signal does not meet setup timing for clock gating input registers of the memory interface signal, a clock gate enable signal may be generated prior to evaluation of the memory enable signal. The clock gate enable signal includes all functions of the memory enable signal and additional conditions because it is generated prior to evaluation of conditions on which the memory enable signal may depend. Pre-evaluated clock gate enable signals may be generated within a processor core and used to clock gate read address registers, write address registers, data input registers, and/or CAM reference address registers of an embedded memory array.