3D Memory Array Layout With Over-Staircase CMOS Drivers
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and performance while minimizing the size and complexity of memory devices due to limitations in control logic device configurations and processing conditions, which impede reductions in size and performance improvements.
Innovation Solution
A novel microelectronic device structure is developed with a first microelectronic device structure that includes global digit lines, multiplexer regions, and vertical stacks of memory cells, where control logic devices are integrated separately in a second microelectronic device structure, reducing the distance between contact structures and enhancing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If control logic devices are integrated within the base control logic structure underlying the memory array, then the memory device can be formed with a unified structure, but the processing conditions (temperatures, pressures, materials) for the formation of the memory array limit the configurations and performance of the control logic devices
Solution Approach 1:
The patent divides the microelectronic device into separate structures: a first microelectronic device structure containing the memory array and a second microelectronic device structure containing the control logic devices. This segmentation allows each structure to be optimized independently with different processing conditions, materials, and configurations, resolving the contradiction between unified structure and device adaptability.
Solution Approach 2:
The control logic devices are extracted from the base control logic structure and placed in a separate second microelectronic device structure. This extraction enables the control logic devices to have different configurations and performance characteristics without being constrained by the memory array formation conditions, while still being electrically connected through interconnect structures.
2Productivity
If the quantities, dimensions, and arrangements of control logic devices are increased to handle higher memory array density, then the control logic can manage more memory cells, but the control logic devices consume more real estate, reducing the memory density of the memory device
Solution Approach 1:
The patent transitions from a two-dimensional planar integration to a three-dimensional stacked architecture where the second microelectronic device structure (control logic) is positioned above the first microelectronic device structure (memory array). This vertical stacking in the third dimension allows high-density memory arrays to be managed by control logic devices without increasing the horizontal footprint, thus maintaining high memory density while handling increased memory cell quantities.
3Area of moving object
If the separation distance between neighboring features is reduced to increase integration density, then more features can be packed into the device, but the processing conditions for memory array formation limit the precision and performance of the control logic devices
Solution Approach 1:
By segmenting the device into separate microelectronic device structures, each can be fabricated with optimized processing conditions appropriate for their specific requirements. The first structure can use processing conditions optimized for high-density memory array formation, while the second structure can use conditions optimized for precise control logic device fabrication, allowing both high integration density and high manufacturing precision to coexist.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures. The microelectronic device further comprises a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising a sub word line driver region comprising complementary metal-oxide-semiconductor (CMOS) circuits vertically overlying and within a horizontal area of the staircase structure, and conductive contact structures vertically extending between steps of the staircase structure and the sub word line driver region. Related memory devices, electronic systems, and methods are also described.