Memory Array Circuit Arrangement with Contiguous CMOS Subarrays
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Solution Overview
Problem
Current memory devices face challenges in optimizing the area for Complementary Metal-Oxide-Semiconductor (CMOS) circuitry, leading to higher power delivery impedance and longer signal propagation due to the splitting of CMOS circuitry across multiple subarrays.
Innovation Solution
The memory architecture is redesigned to increase the contiguous area for CMOS circuitry by strategically placing word line driver regions, digit line driver regions, and interconnects, allowing for lower impedance power delivery and shorter signal propagation without splitting the CMOS circuitry area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If CMOS circuitry is split across multiple subarrays, then memory device area is optimized, but power delivery impedance increases and signal propagation length increases
Solution Approach 1:
The memory device is divided into multiple subarrays, each with its own dedicated driver circuitry (word line drivers, digit line drivers, sense amplifiers). This segmentation allows each subarray to be independently controlled while maintaining optimized power delivery and signal propagation within each segment, preventing the degradation that would occur with a single large divided circuitry area.
2Area of stationary object
If CMOS circuitry is split across multiple subarrays, then memory device area is optimized, but signal propagation distance increases
Solution Approach 1:
Driver circuitry and memory cells are segmented into closely coupled subarrays, where each subarray contains its own driver circuits positioned adjacent to the memory cells it controls. This minimizes the physical distance signals must travel between drivers and memory cells, reducing propagation delay despite the overall device area being large.
Solution Approach 2:
The patent employs three-dimensional stacking with multiple interconnection layers (first interconnect layer, second interconnect layer, third interconnect layer) to route signals vertically and horizontally. This multi-dimensional interconnect architecture reduces signal propagation distance by providing direct vertical pathways through the stack, avoiding long horizontal routes that would be necessary in a planar layout.
3Reliability
If CMOS circuitry area is increased contiguously, then power delivery impedance decreases and signal propagation shortens, but memory device area optimization is reduced
Solution Approach 1:
Driver circuitry and memory cells are merged into integrated subarray blocks where control circuits are positioned immediately adjacent to the memory cells they control. This merging creates locally optimized circuits with minimal interconnect distance, achieving low impedance power delivery and short signal propagation while maintaining high area efficiency through the use of shared interconnect resources across multiple subarrays.
Solution Approach 2:
The patent utilizes multiple stacked interconnect layers to route power and signal lines in three dimensions. This vertical stacking allows for dense, short interconnect paths between driver circuits and memory cells without increasing the planar footprint, thereby maintaining area efficiency while achieving low impedance and short propagation distances.
Data Source
AI summary
Methods, systems, and devices for memory array circuit arrangement are described. A memory device may include a memory subarray, which may include a complementary metal oxide semiconductor (CMOS) circuitry under array (CuA) circuitry area and a word line driver region (e.g., word line driver circuitry) or a digit line driver region (e.g., digit line driver circuitry, sense amplifier circuitry multiplexed with the digit line driver circuitry). The memory subarray may include a first interconnect extending in a first and traversing at least a first portion of the CuA circuitry area of the memory subarray. The first interconnect may be coupled with the first portion of the CuA circuitry area and a first interconnection layer. Additionally, each memory subarray may include a second interconnect extending in a second direction and traversing at least a second portion of the CuA circuitry area of the memory subarray.