Memory Array Column Failure Detection via Row Adjacency Analysis
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Solution Overview
Problem
Conventional memory built-in self-test (mBIST) systems fail to detect column failures effectively due to the complexity and design overhead of tracking column failing addresses, often requiring numerous repair attempts with limited row redundancies, leading to unrepairable flags when true column failures occur.
Innovation Solution
The system detects column failures by identifying a threshold number of failing rows in series and determines if adjacent rows have also failed, generating a signal indicative of a column failure through error registers and adjacency units, allowing for timely identification of unrepairable conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional mBIST systems track column failing addresses to detect column failures, then column failure detection capability is improved, but device complexity and design overhead increase significantly
Solution Approach 1:
The patent segments the failure detection task by separating row failure detection from column failure detection. Instead of tracking column addresses directly, the system detects row failures and uses their spatial distribution pattern (adjacency) to infer column failures. This segmentation eliminates the need for complex column address tracking while maintaining detection capability.
Solution Approach 2:
The patent inverts the conventional approach by not directly detecting column failures through column address tracking. Instead, it detects row failures and infers column failures from the pattern of adjacent row failures. This inversion simplifies the detection mechanism by working backwards from observable row failures to inferred column failures.
2Ease of repair
If conventional mBIST systems attempt numerous repairs with limited row redundancies, then repair coverage is improved, but time consumption increases and unrepairable flags are generated for true column failures
Solution Approach 1:
The patent performs preliminary detection of column failures by analyzing the adjacency pattern of row failures before initiating repair attempts. By detecting that multiple adjacent rows have failed (indicating a column failure), the system can identify unrepairable conditions early, avoiding wasted time on repetitive repair attempts that would inevitably fail.
Solution Approach 2:
The patent implements a feedback mechanism where the detection of adjacent row failures provides information about column failure conditions. This feedback allows the system to determine when repairs are futile (true column failures) and stop attempting repairs, thereby reducing time loss while maintaining appropriate repair coverage for repairable row failures.
Data Source
AI summary
Microelectronic device testing, and related methods, devices, and systems, are described herein. A device may include a memory array including a number of rows and a number of columns. The memory device may further include circuitry coupled to the memory array. The circuitry may be configured to perform a testing operation on each row of the number of rows to detect: a first fail of a first row of the number of rows; and a set of additional fails associated with a set of rows of the number of rows. The circuitry may also be configured to determine whether the set of rows is adjacent the first row. Further, in response to determining that the set of rows is adjacent the first row, the circuitry may be configured to generate a signal indicative of a failure of a column of the number of columns.