3D Memory Array With Column Selection Switches
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Solution Overview
Problem
Traditional two-dimensional memory arrays face limitations in memory density and cost due to increased RC loading and area penalties in three-dimensional memory structures, particularly with the rise in the number of bit lines, source lines, and word lines, which affect pre-charge and sensing speed.
Innovation Solution
A new three-dimensional memory array structure is introduced, where memory cells are arranged in multiple columns with selection switches that allow global bit lines and source lines to be selectively connected to local lines, reducing RC loading and the number of word line decoders, thereby improving area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory structure is utilized for higher memory cell density, then memory density is improved, but RC loading increases and area penalty occurs
Solution Approach 1:
The memory array is divided into multiple columns with local bit lines and local source lines serving each column. Selection switches are placed at column boundaries to selectively connect to global bit lines and global source lines. This segmentation reduces RC loading by limiting the capacitance that each global line must drive, while maintaining high memory density through the three-dimensional columnar structure.
Solution Approach 2:
The patent transitions from traditional two-dimensional memory arrays to a three-dimensional structure with multiple columns stacked vertically. Memory cells are arranged in columns extending in the vertical direction, with selection switches positioned at different heights. This dimensional change increases memory cell density without proportionally increasing the number of global interconnect lines, thereby reducing RC loading per memory cell.
2Quantity of substance
If the number of bit lines, source lines, and word lines is increased for higher memory capacity, then memory capacity is improved, but pre-charge and sensing speed deteriorate
Solution Approach 1:
Local bit lines and local source lines are introduced to serve individual columns, with selection switches enabling selective connection to global bit lines and global source lines. This segmentation allows parallel operation of multiple columns while limiting the RC loading on each global line, thereby maintaining pre-charge and sensing speed even as memory capacity increases through additional columns.
Solution Approach 2:
Selection switches act as intermediaries between local data lines (serving memory cells) and global data lines (connecting to sense amplifiers). These switches enable selective connection, allowing multiple local lines to share global lines in a time-multiplexed manner. This intermediary structure increases memory capacity without requiring proportional increases in global interconnect count, preserving signal transmission speed.
3Area of stationary object
If more word line decoders are added to support increased number of word lines, then memory array coverage is improved, but area efficiency deteriorates
Solution Approach 1:
Multiple columns are organized under shared global bit lines and global source lines, with selection switches enabling selective activation. This merging approach allows a reduced set of decoders to control multiple columns simultaneously, improving area efficiency while maintaining comprehensive memory array coverage through the three-dimensional columnar structure.
Solution Approach 2:
Global bit lines and global source lines serve multiple columns universally, with selection switches enabling dynamic reconfiguration. A single global line can be connected to different columns at different times, allowing fewer decoders to manage a larger memory array. This multi-functional approach increases memory array coverage without proportionally increasing decoder count.
Data Source
AI summary
A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.