Memory Array Compare Operations Using Sensing Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in performing compare operations efficiently, as they often require data transfer out of the memory array and external processing, which can affect chip size and memory density due to incompatible pitch rules between memory cells and processing resources.
Innovation Solution
The implementation of sensing circuitry within the memory array that allows for precharging of input/output lines and selective activation of access lines to determine if data matches a compare value without transferring data via a bus, enabling compare and report operations directly within the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred out of the memory array for external processing, then compare operations can be performed, but chip size increases and memory density decreases
Solution Approach 1:
The patent combines the compare operation functionality with the memory array by integrating sensing circuitry that can perform comparisons directly within the memory structure. The sensing circuitry is merged with existing memory components (bit lines, word lines, memory cells) to enable compare operations without requiring separate external processing units, thereby avoiding additional chip area while maintaining compare functionality
Solution Approach 2:
The sensing circuitry in the memory array is designed to perform multiple functions: traditional data sensing/readout operations and compare operations. By making the sensing circuitry universal, it can handle both standard memory access tasks and comparison tasks, eliminating the need for dedicated external compare processing hardware and thus preventing chip size expansion
2Productivity
If data is transferred out of the memory array for external processing, then compare operations can be performed, but memory density decreases
Solution Approach 1:
The compare operation functionality is merged into the memory array structure itself, utilizing existing sensing circuitry and signal lines. This integration allows compare operations to be performed using the same physical infrastructure as data access operations, preventing any reduction in memory density while adding compare capability
Solution Approach 2:
The memory array performs compare operations on its own data using its internal sensing circuitry, without requiring external processing assistance. The sensing circuitry detects voltage changes on bit lines that indicate matches between stored data and compare values, enabling the memory array to self-perform compare operations without external intervention or additional processing resources
3Measurement precision
If sensing circuitry is used to detect voltage changes for compare operations, then match determination is achieved, but operational complexity increases
Solution Approach 1:
The sensing circuitry monitors voltage changes on bit lines during compare operations and uses this feedback to determine matches. When a memory cell matches the compare value, it creates a detectable voltage change that feeds back to the sensing circuitry, which then signals the match condition. This feedback mechanism enables accurate match detection while keeping the operational sequence straightforward and manageable
Data Source
AI summary
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.