Memory Array Conductor Tier Galvanic Corrosion Protection
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Solution Overview
Problem
The existing NAND memory architecture faces issues with lateral etching of conductively-doped polysilicon due to galvanic reaction/corrosion when silicide is exposed, leading to failed circuitry during the etching process of vertically-stacked memory cells.
Innovation Solution
Incorporating an intervening metal material with a reduction potential less than 0.7V away from the upper conductor material, such as TiN or WN, between the upper conductor material and the lower metal material, to reduce or eliminate galvanic reaction/corrosion during the etching process, thereby protecting the polysilicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If vertically-stacked memory cells are etched through the stack and conductively-doped polysilicon to the silicide, then memory cell formation is achieved, but lateral etching of the polysilicon occurs due to galvanic reaction/corrosion
Solution Approach 1:
An intervening metal material layer is introduced between the upper conductor material (silicide) and the lower metal material to act as a protective intermediary. This layer prevents direct galvanic interaction between the silicide and etching chemicals, thereby eliminating lateral etching of the conductively-doped polysilicon while allowing vertical etching to proceed to form memory cells.
Solution Approach 2:
The intervening metal material is deposited in advance before the etching process to preemptively protect the polysilicon from galvanic corrosion. This preliminary protective action prevents the harmful lateral etching from occurring during subsequent processing steps.
2Reliability
If an intervening metal material layer is added between upper conductor material and lower metal material, then galvanic reaction/corrosion is reduced or eliminated, but device structure complexity increases
Solution Approach 1:
The intervening metal material layer is designed with specific parameter constraints: its thickness is controlled to be between 5-50 nanometers, and its reduction potential is selected to be within 0.7V of the upper conductor material. These parameter specifications ensure protective function while minimizing the impact on overall device complexity.
Solution Approach 2:
The conductor tier is structured as a composite of multiple material layers (upper conductor material, intervening metal material, lower metal material) where each layer serves a specific function. This composite structure achieves both electrical conductivity and corrosion protection without requiring fundamentally new device architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces lateral etching and corrosion, ensuring the integrity of the memory cell circuitry and preventing failures associated with galvanic reactions, thus enhancing the reliability of the memory array formation process.
Implementation Method 1
lateral etching of the polysilicon upon exposure of the silicide due to galvanic reaction/corrosion
Data Source
AI summary
A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and structure independent of method are disclosed.