3D Memory Array Connection Layout for Shorter Signal Paths
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high storage capacity and efficient operating speed due to limitations in the design of memory arrays and connection regions.
Innovation Solution
A memory device with a stacked structure featuring conductive layers and insulating layers alternately stacked, including a connection region with a staircase region, unprocessed region, bottom isolating member, and common wall, which reduces resistance and capacitance by shortening the transmission path for current/voltage between array regions, and allows for electrical connection through vertical contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a connection region is disposed between first and second array regions, then the transmission path for current/voltage is shortened and operating speed is improved, but the device complexity increases due to additional structural elements (staircase region, unprocessed region, common wall, isolating sidewall)
Solution Approach 1:
The connection region is segmented into distinct functional zones including a staircase region with stepped profile, an unprocessed region with isolating sidewall, and a common wall region. This segmentation allows each zone to perform its specific function (current path, isolation, structural support) while collectively achieving the overall goal of shortened transmission path and improved operating speed without excessive complexity
Solution Approach 2:
The staircase region introduces a stepped profile in the vertical dimension, creating multiple levels for conductive layers to connect between first and second array regions. This dimensional approach shortens the horizontal transmission path by utilizing vertical stacking, thereby improving operating speed while managing structural complexity through organized multi-level architecture
2Quantity of substance
If the staircase region volume is minimized, then storage capacity is improved, but the ease of manufacture decreases due to tighter spacing requirements for conductive layers and isolating structures
Solution Approach 1:
The isolating sidewall is positioned specifically within the unprocessed region to provide localized electrical isolation between the staircase region and array regions. This localized isolation approach minimizes the overall volume required for the connection region while ensuring proper electrical separation, thereby improving storage capacity without significantly compromising manufacturing ease
Solution Approach 2:
The common wall is nested within the connection region structure, serving dual purposes as both a structural support element and a pathway for conductive layers. This nesting approach optimizes space utilization in the connection region, allowing for reduced staircase region volume and improved storage capacity while maintaining manufacturability through integrated design
Data Source
AI summary
A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a top isolating member and a common wall, wherein the unprocessed region extends along the first direction, the staircase region is adjacent to a first side of the unprocessed region, the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region. The top isolating member extends along the first direction to separate the conductive layers disposed in a top portion of the stacked structure.