Memory Array Node Contact Etching for Boundary Hole Consistency
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Solution Overview
Problem
The inconsistency of node contact holes formed in the boundary and inner regions of a memory array due to Pattern Loading Effects in the etching process, leading to complex manufacturing processes and low chip output efficiency.
Innovation Solution
A method where a cap material layer is formed over bit lines and spacing lines, allowing for the etching of node contact holes in a single process using a plasma etching apparatus, with the cap layer acting as a mask to remove the first insulating material only in the inner region, thereby forming consistent node contact holes while maintaining the first insulating material as dummy contact holes in the boundary region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If node contact holes are formed in both inner and boundary regions using the same process, then the manufacturing process is simple, but the consistency of node contact holes is poor due to Pattern Loading Effects
Solution Approach 1:
The memory array region is divided into an inner region and a boundary region, with different etching processes applied to each region. This segmentation allows the pattern loading effects to be addressed differently in each region, improving node contact hole consistency while maintaining overall process simplicity.
Solution Approach 2:
Different etching conditions are applied to different regions: the inner region uses standard etching while the boundary region uses adjusted etching parameters to compensate for pattern loading effects. This local quality approach ensures consistent node contact hole formation across regions with different pattern densities.
2Manufacturing precision
If boundary region contact holes are converted to dummy contact holes to improve consistency, then node contact hole consistency is improved, but the manufacturing process becomes complex and chip output efficiency decreases
Solution Approach 1:
The etching process is made dynamic by adjusting etching parameters based on the region being processed. The boundary region receives modified etching conditions during the same process flow, eliminating the need for separate dummy contact hole formation steps and maintaining high productivity while ensuring consistency.
3Manufacturing precision
If multiple etching processes are used for inner and boundary regions, then node contact hole consistency is improved, but the manufacturing process complexity increases
Solution Approach 1:
The etching processes for the inner region and boundary region are merged into a single integrated process flow. By combining the processes and using regional parameter adjustments rather than separate process steps, the methodology reduces manufacturing process complexity while maintaining node contact hole consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by allowing all etching operations to be performed in a single machine, reducing costs and improving chip output efficiency while ensuring good electrical quality by maintaining consistency in node contact holes.
Implementation Method 1
An etching process is performed to form node contact holes, which includes the following operations. The cap material layer is etched to form a cap layer covering the bit lines, the spacing lines and the first insulating material in the boundary region. The first insulating material in the inner region is removed by etching with the cap layer as a mask to from the node contact holes.
Data Source
AI summary
A method for manufacturing a semiconductor device includes following operations. A substrate is provided, including memory array region. A plurality of bit lines are formed in memory array region. First insulating material is filled between the plurality of bit lines. A plurality of trenches intersecting with bit lines are provided in first insulating material. Memory array region includes inner region and boundary region outside same. Second insulating material is filled in trenches to form spacing lines. Second insulating material is also deposited above bit lines, spacing lines and first insulating material to form cap material layer. Etching process is performed to form node contact holes, including following operations. Cap material layer is etched to form cap layer covering bit lines, spacing lines and first insulating material in boundary region. First insulating material in inner region is removed by etching with cap layer as mask to from node contact holes.