3D Memory Array Stacking With Decoupled Control Logic Formation
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Solution Overview
Problem
Conventional microelectronic device designs, particularly in memory devices, face challenges in reducing size and improving performance due to processing conditions and configurations of control logic devices, which limit the miniaturization and efficiency of memory arrays.
Innovation Solution
The method involves forming a microelectronic device structure with a memory array region over a semiconductive base structure, attaching it to a base structure, and then forming a control logic region and interconnect region to enable control logic devices to communicate with memory cells without being constrained by initial processing conditions, using conductive and insulative materials in specific configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If control logic devices are formed under the same processing conditions as memory arrays, then manufacturing process is simplified, but device performance and configuration flexibility are limited
Solution Approach 1:
The patent divides the device into two distinct regions: a memory array region formed under first processing conditions and a control logic region formed under second processing conditions. This segmentation allows each region to be optimized independently for its specific functional requirements while maintaining separate fabrication processes that do not interfere with each other.
Solution Approach 2:
The patent applies different processing conditions to different regions of the device. The memory array region receives first processing conditions optimized for memory cell formation, while the control logic region receives second processing conditions optimized for logic device performance. This local differentiation enables each region to achieve its optimal characteristics without compromise.
2Ease of manufacture
If control logic devices are formed under the same processing conditions as memory arrays, then fabrication is easier, but device miniaturization is impeded
Solution Approach 1:
By segmenting the fabrication process into separate steps for memory array formation and control logic formation, the patent enables independent optimization of each region's dimensions and layout. This allows the control logic region to be miniaturized using techniques specific to logic devices without being constrained by memory array processing requirements.
3Device complexity
If control logic devices are formed under the same processing conditions as memory arrays, then process complexity is reduced, but device performance is limited
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming the memory array region under first processing conditions, then forming the control logic region under second processing conditions. This segmentation resolves the contradiction by allowing high-performance optimization in each region while managing overall process complexity through systematic separation of fabrication steps.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure. The microelectronic device structure comprises a semiconductive base structure, and a memory array region vertically overlying the semiconductive base structure and comprising memory cells. The microelectronic device structure is attached to a base structure. A portion of the semiconductive base structure is removed after attaching the microelectronic device structure to a base structure. A control logic region is formed vertically over a remaining portion of the semiconductive base structure. The control logic region comprises control logic devices in electrical communication with the memory cells of the memory array region. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.