Memory Array Output Block for Differential Current Readout
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Solution Overview
Problem
Existing artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of high computational parallelism and energy efficiency, with CMOS-implemented synapses being too bulky for large-scale neural networks.
Innovation Solution
Utilizing non-volatile memory arrays as synapses in artificial neural networks, allowing for individual programming, erasing, and reading of memory cells without affecting others, and enabling continuous analog programming for precise tuning of synapse weights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS analog circuits are used for synapses in artificial neural networks, then the neural network can perform computation, but the synapses become too bulky for large-scale implementations
Solution Approach 1:
The patent replaces traditional CMOS analog circuit implementations of synapses with non-volatile memory cells (such as flash memory cells). This substitution eliminates the need for complex multiplication and addition logic circuits while maintaining the synaptic function of storing weight values and performing analog computation through charge storage on floating gates.
Solution Approach 2:
The non-volatile memory cells serve multiple functions: they store weight values (synaptic weights), perform analog multiplication through their electrical characteristics, and provide non-volatile storage. This multi-functionality reduces the overall system complexity and area compared to dedicated analog circuit implementations.
2Productivity
If digital supercomputers or GPU clusters are used to achieve high computational parallelism, then neural network performance improves, but energy efficiency deteriorates
Solution Approach 1:
The non-volatile memory array performs computation in-place without requiring separate processing units. The memory cells themselves execute the multiplication and addition operations through their inherent electrical characteristics, eliminating the need to move data between storage and processing units, thus reducing energy consumption while maintaining high parallelism.
Solution Approach 2:
The patent merges the storage and computation functions into a single non-volatile memory array. Traditional systems separate memory (storage) and processors (computation), but this integration allows the same hardware structure to perform both functions, achieving high computational parallelism with reduced energy overhead.
3Area of stationary object
If non-volatile memory arrays are used as synapses, then energy efficiency and integration density improve, but the complexity of individual cell programming and reading increases
Solution Approach 1:
The patent divides the neural network computation into distinct phases: programming phase (where weight values are written to memory cells) and reading/computation phase (where the memory cells perform analog multiplication). This segmentation allows complex programming operations to be performed once during training, followed by simpler read operations during inference, reducing the overall operational complexity.
Solution Approach 2:
The patent introduces reference memory cells and sensing circuits as intermediaries to simplify the reading process. These intermediary components convert the analog signals from the memory cells into readable formats without requiring complex direct readout circuits, thus reducing the overall system complexity while maintaining high integration density.
Data Source
AI summary
In one example, a circuit comprises a current-to-voltage converter to convert a first current into a first voltage and to convert a second current into a second voltage, where the first current and the second current are differential currents; a level shifter to convert the first voltage into a third voltage and to convert the second voltage into a fourth voltage; and an analog-to-digital converter to convert the third voltage and the fourth voltage into a set of output bits.