Memory Array Data Line Selection via Multiplexer Switching
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Solution Overview
Problem
The increasing density of memory cells in memory devices poses challenges in designing efficient circuitry for accessing and operating these cells, particularly in managing signal lines and voltage biases during read, programming, and erase operations.
Innovation Solution
The implementation of a memory device architecture that includes separate switching circuits and bias units with multiple gates, allowing for selective coupling of signal lines to different voltages and decoupling during operations to reduce parasitic capacitance and improve operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased for a given device area, then storage capacity is improved, but circuit design complexity increases
Solution Approach 1:
The memory array is divided into multiple blocks, with each block containing a subset of memory cells. This segmentation allows the complex memory array to be managed in smaller, more manageable units, reducing the overall circuit design complexity while maintaining high memory cell density.
Solution Approach 2:
Multiplexer circuits are introduced as intermediary components between the memory cells and sense amplifiers. These multiplexers selectively couple specific memory cells to sense circuits, acting as mediators that simplify the direct connection complexity in high-density memory arrays.
2Quantity of substance
If memory cell density is increased, then storage capacity is improved, but access efficiency deteriorates
Solution Approach 1:
The memory array is segmented into blocks, and each block can be independently accessed. This segmentation enables parallel access operations across different blocks, maintaining access efficiency even as overall memory cell density increases.
Solution Approach 2:
The multiplexer circuits dynamically select and couple specific memory cells to sense amplifiers based on access requirements. This dynamic switching capability enables efficient access to specific memory cells within high-density blocks without requiring all cells to be accessed simultaneously.
3Area of stationary object
If device area is reduced for high density, then compactness is improved, but capacitance between lines increases
Solution Approach 1:
The harmful capacitance between data lines and sense amplifier lines is extracted and managed through selective coupling mechanisms. The multiplexer circuits enable specific lines to be coupled only when needed, effectively removing unwanted capacitive interactions from the system.
Solution Approach 2:
The circuit design preemptively addresses capacitance issues by implementing selective coupling through multiplexers. This preliminary anti-action prevents unwanted capacitance from affecting memory operations before it can cause problems, rather than attempting to correct it after the fact.
Data Source
AI summary
Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.