Memory Array Defect Detection Circuit
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Solution Overview
Problem
Defects in memory cell arrays during manufacturing and design pose challenges in determining the types and locations of defects effectively, necessitating a reliable detection method for semiconductor memory technologies.
Innovation Solution
A memory array detection circuit comprising a write circuit, a read circuit, and a data compression circuit that writes initial data into each memory cell, reads the data, and compares it to detect defects by identifying identical or non-identical data across memory cells, with output circuits indicating defectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional defect detection methods are used for memory arrays, then the detection process becomes complex and time-consuming, but the ability to accurately identify defect types and locations is compromised
Solution Approach 1:
The memory array is divided into multiple sub-arrays, and the detection process is segmented into distinct phases: writing initial data, reading data, compressing read data, and comparing results. This segmentation simplifies the overall detection process while maintaining accurate defect identification capability.
Solution Approach 2:
Initial data is written into all memory cells before the detection process begins. This preliminary action prepares the memory array in a known state, enabling systematic comparison and defect identification without requiring complex detection algorithms during the actual testing phase.
2Reliability
If comprehensive defect detection is performed across the entire memory array, then all defects can be identified, but the detection time and resources increase significantly
Solution Approach 1:
The detection method extracts and focuses on comparing specific data patterns from read operations. By extracting only the essential comparison information rather than analyzing every possible defect parameter, the system achieves comprehensive defect detection with reduced time and resource requirements.
Solution Approach 2:
The detection approach changes the parameter being measured from comprehensive physical defect analysis to simple data equality comparison. This parameter transformation enables rapid detection while maintaining reliability, as defective cells will produce different data values compared to functional cells.
3Measurement precision
If detailed comparison of all read data is performed to ensure accurate defect detection, then defect identification precision improves, but the computational complexity and processing time increase
Solution Approach 1:
The method uses data copying and comparison where read data is compared against expected patterns or against each other. This copying approach enables precise defect identification through simple equality checks rather than complex analysis, maintaining high precision while improving detection efficiency.
Solution Approach 2:
The detection performs a sufficient level of comparison action to identify all defects without over-analyzing. By performing partial comparison (checking data equality) rather than exhaustive analysis of all possible defect characteristics, the system achieves accurate defect identification with improved processing efficiency.
Data Source
AI summary
A memory array detection circuit includes: a memory array including multiple memory cells; a write circuit, connected to the memory array and configured to write same initial data into each memory cell of the memory array; a read circuit, connected to the memory array and configured read the data stored in each memory cell of the memory array; and a data compression circuit, connected to the read circuit and configured to: compare the data read from the multiple memory cells, and detect whether the memory array is defective according to whether the read data are identical.