Memory Array Reconfiguration for Reduced-Density Defect Salvage
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Solution Overview
Problem
Existing memory devices face challenges in fully utilizing arrays due to defects, leading to high waste and reduced revenue, as current repair methods are limited and do not allow sufficient flexibility in reconfiguring functional portions for reduced density operation.
Innovation Solution
Implementing a fuse array and mode register to programmatically select which banks and rows of the memory array are utilized, allowing for flexible operation in reduced density modes such as half-density or quarter-density, even if some regions are defective.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional repair methods using redundant rows are used, then some defective rows can be repaired, but the array cannot be fully utilized when too many rows are defective
Solution Approach 1:
The memory array is divided into multiple banks, and each bank can be independently configured and utilized. This segmentation allows the system to selectively enable or disable specific banks based on defect locations, enabling partial array operation when complete array functionality is compromised.
Solution Approach 2:
The patent implements dynamic reconfiguration capabilities through mode registers and control logic that allow the memory array to adapt its operational configuration at runtime. The system can dynamically switch between different bank groupings and density modes (full density, half density, quarter density) based on detected defects, providing flexibility that static repair methods cannot achieve.
2Reliability
If the array is rejected when too many defective rows exist, then quality standards are maintained, but revenue is reduced and waste increases
Solution Approach 1:
The patent converts the harmful effect of defects into a beneficial outcome by implementing defect-tolerant operation modes. Instead of rejecting defective arrays, the system identifies and isolates defective regions, then reconfigures to utilize only functional portions, thereby transforming potential waste into usable memory capacity.
Solution Approach 2:
The system changes operational parameters such as density mode (full, half, quarter density) and bank group configuration based on defect characteristics. By adjusting these parameters, the system optimizes array utilization while maintaining acceptable quality standards, preventing rejection of arrays that can still provide useful functionality.
3Adaptability or versatility
If flexible reconfiguration is implemented to utilize functional portions, then waste is reduced, but device complexity increases
Solution Approach 1:
The patent implements multi-functional control logic that handles multiple tasks: defect detection, bank selection, density mode switching, and address remapping. This universal control structure reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving high reconfiguration flexibility.
4Ease of repair
If redundant rows are used for repair, then some defects can be corrected, but the ability to operate in reduced density modes is limited
Solution Approach 1:
The patent extends repair capabilities from the traditional row-replacement dimension to include bank-level and bank-group-level reconfiguration dimensions. By operating in additional dimensional spaces (different density modes, different bank groupings), the system achieves versatile defect mitigation that goes beyond simple redundant row replacement.
Data Source
AI summary
In some examples, a fuse array, a mode register, or a combination thereof, is programmed to select which banks and/or rows are to be utilized in a reduced density mode of a memory device. In some examples, an additional fuse or other programmable device is used to indicate memory device is operating in a reduced density mode. The information from the fuse array, mode register, or combination thereof, is provided to an array utilization circuit, which uses the information to access the utilized portions of the memory array. In some embodiments, the array utilization circuit may map a smaller external row address space to a larger internal row address space when a memory device is in a reduced density mode.