Memory Array Digital MAC Using 1.5-Bit Cells for Accurate AI Compute
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Solution Overview
Problem
Semiconductor memory devices face challenges in AI computations due to misjudgment of computation results from current distribution overlaps, increased resource and time consumption with larger bit computations, and errors in multi-level cell reading operations, which degrade computation accuracy and speed.
Innovation Solution
Implementing digital MAC-operations with a memory array that reduces threshold voltage distribution states and employs pipelined computation schedules and majority group-counting, using 1.5-bit multi-level cells and a combination of MSB and LSB vectors to enhance the accuracy and speed of computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If analog MAC operation is performed in memory array, then computation speed is improved, but computation accuracy deteriorates due to current distribution overlaps
Solution Approach 1:
The patent replaces the analog current-based MAC operation with a digital voltage-based MAC operation. Instead of using analog currents that overlap and cause accuracy issues, the invention uses digital voltage levels (e.g., 0V and Vdd) to represent binary data and performs MAC operations through digital logic circuits, thereby eliminating the accuracy problems while maintaining computational efficiency
Solution Approach 2:
The patent changes the fundamental operating parameters from analog current domains to digital voltage domains. By transforming the data representation from continuous analog currents to discrete digital voltages, and changing the operation mode from analog accumulation to digital computation, the system achieves both high speed and high accuracy
2Quantity of substance
If multi-level cells (MLC) are used to store data, then storage capacity is improved, but reading accuracy deteriorates due to threshold voltage distribution narrowing
Solution Approach 1:
The patent extracts only the most significant bits (MSB) from the MLC threshold voltage distribution for computation purposes. By focusing on the MSB portion of the voltage distribution, the system achieves sufficient accuracy for MAC operations while utilizing the high storage capacity of MLC, effectively separating the storage function from the computation function
Solution Approach 2:
The patent changes the parameter used for computation from the full threshold voltage distribution to specifically the MSB portion. This parameter transformation allows the system to leverage the high-density storage of MLC while maintaining reading accuracy by operating on a simplified, more distinct voltage parameter
3Loss of information
If bit line setups are performed multiple times for multi-bit data, then computation completeness is improved, but computation speed deteriorates due to repeated setup-time consumption
Solution Approach 1:
The patent merges multiple bit operations into a single parallel operation. By loading all necessary multi-bit data into the memory array simultaneously and performing the MAC operation in one unified process, the system eliminates the need for repeated bit line setups and achieves both complete computation and high speed
Solution Approach 2:
The patent maintains continuous useful action by performing the entire MAC operation for multi-bit data in a single uninterrupted process. The memory array continuously processes all bits simultaneously without idle setup periods between bit operations, maximizing computational throughput and efficiency
Data Source
AI summary
A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.