3D Memory Array Channel Strings With Dopant-Diffused Vertical Coupling

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Solution Overview

Problem

Existing memory array architectures face challenges in efficiently forming vertically-stacked memory cells with reliable electrical connections and structural integrity, particularly in NAND architectures, which affect data retention and access times.

Innovation Solution

A method involving 'gate-last' or 'replacement-gate' processing is employed to form memory arrays with vertically-stacked memory cells, using alternating conductive and insulative tiers, and forming conductive strings with enhanced conductivity through dopant diffusion into channel materials, ensuring stable electrical coupling and structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertically-stacked memory cells are formed using conventional methods, then memory array structure is achieved, but electrical connections and structural integrity are unreliable

Engineering Contradiction:

Improveelectrical connections and structural integrityVSAvoidfabrication complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The method performs preliminary actions by forming alternating conductive and insulative tiers before forming the channel material strings. This preliminary structuring ensures that electrical connections are established in advance, improving reliability of vertical connections while maintaining manufacturability through systematic fabrication steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The memory array is segmented into vertically-stacked memory cells with alternating conductive and insulative tiers. This segmentation creates discrete, manageable units with defined electrical boundaries, improving structural integrity and electrical connection reliability while enabling scalable fabrication processes.

Inventive Principle:

Principle #1Segmentation

2Reliability

If dopant diffusion is used to enhance conductivity, then electrical conductivity improves, but manufacturing process complexity increases

Engineering Contradiction:

Improveelectrical conductivityVSAvoidprocessing steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The method changes material parameters by introducing dopant materials into the channel material strings and heating to diffuse dopants. This parameter change enhances electrical conductivity of the vertical strings while the heating step integrates smoothly into existing fabrication processes, managing complexity through thermal processing.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The dopant material acts as an intermediary substance that, when diffused into the channel material, enhances electrical conductivity. This intermediary approach allows conductivity improvement without fundamentally changing the channel material composition, maintaining process compatibility.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of time

If vertically-stacked architecture is implemented, then data retention and access times improve, but fabrication reliability challenges increase

Engineering Contradiction:

Improvedata access timeVSAvoidfabrication reliability

Core Design Contradiction:

Loss of timeVSEase of manufacture

Solution Approach 1:

The patent transitions to a three-dimensional vertically-stacked architecture where memory cells are arranged in vertical strings rather than planar arrays. This dimensional change improves data access time by enabling parallel access to multiple memory cells through vertical bitlines, while fabrication reliability is maintained through alternating conductive/insulative tier formation.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The vertically-stacked structure uses composite material arrangements with alternating conductive and insulative tiers surrounding channel material strings. This composite structure provides both the vertical connectivity needed for fast access and the structural integrity required for reliable fabrication.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the conductivity and structural integrity of vertically-stacked memory cells, improving data retention and access times, while allowing for scalable and reliable memory array fabrication.

Implementation Method 1

The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces

Methodology Applied

Scientific EffectDopant diffusion: Diffusion

Data Source

PatentUS20260006791A1Integrated Circuitry Comprising a Memory Array Comprising Strings of Memory Cells and Method Used in Forming a Memory Array Comprising Strings of Memory Cells

Publication Date: 2026.01.01 MICRON TECHNOLOGY INC

AI summary

A liner is formed laterally-outside of individual channel-material strings in one of first tiers and in one of second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.