Memory Array Word-Line Driver Sharing for Faster Read Signals
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Solution Overview
Problem
Existing resistive random access memory (RRAM) devices face challenges with area overhead and signal transmission speed due to the use of numerous elements in write word line drivers, leading to stress concerns and significant resistor-capacitor (RC) loading effects.
Innovation Solution
Implementing a global write word line driver for multiple memory arrays and local read word line drivers for individual arrays, reducing the overall area of word line drivers and minimizing RC loading effects, thereby accelerating signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If numerous elements are used in write word line drivers, then write functionality is achieved, but area overhead increases and RC loading effects worsen
Solution Approach 1:
The patent merges the write word line driver functionality into a global driver that serves multiple memory arrays simultaneously. Instead of having separate write word line drivers for each array (which would consume excessive area), a single global write word line driver is implemented to control word lines across multiple arrays, thereby reducing area overhead while maintaining write functionality.
Solution Approach 2:
The global write word line driver is designed to perform universal write operations across multiple memory arrays. This multi-functional driver can selectively activate word lines in different arrays based on decode signals, enabling one driver to fulfill the role of multiple drivers and significantly reducing the overall area required for write functionality.
2Reliability
If numerous elements are used in write word line drivers, then write functionality is achieved, but signal transmission speed decreases due to RC loading effects
Solution Approach 1:
By merging multiple write word line driver functions into a single global driver, the total number of driver elements connected to each word line is reduced. This decreases the RC loading effect on individual word lines, thereby improving signal transmission speed and reducing delays in write operations.
3Adaptability or versatility
If separate write word line drivers are used for each memory array, then individual control is achieved, but device complexity increases
Solution Approach 1:
The global write word line driver incorporates decoding logic that enables it to selectively control word lines in different memory arrays based on input signals. This universal driver can adapt to control any targeted array individually or collectively, providing the same level of individual control as separate drivers but with reduced overall device complexity through consolidation.
4Area of stationary object
If global write word line driver is implemented, then area overhead is reduced, but control signal routing complexity increases
Solution Approach 1:
The control signals for the global write word line driver are segmented and distributed to different memory array sections through decode logic. This segmentation allows the single global driver to control multiple arrays independently by activating specific signal paths, thereby managing routing complexity systematically while maintaining area efficiency.
Data Source
AI summary
A memory device is provided. The memory device includes multiple first memory arrays, a first write word line driver, and multiple first read word line drivers. Each of the first read word line drivers is coupled to one array in the first memory arrays. A selected one in the first read word line drivers generates a first word line voltage to a corresponding array in the first memory arrays in a first read operation. A first write word line driver is coupled to at least two drivers in the first read word line drivers, and generates a second word line voltage to the first memory arrays in a first write operation. The second word line voltage is greater than the first word line voltage.