Memory Array ECC Circuitry with Multiplexer-Based Syndrome Generation
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Solution Overview
Problem
Conventional memory cell arrays face challenges in improving data reliability due to errors caused by alpha particles and random defects, which are not effectively addressed by existing ECC techniques, and column redundancy implementations are cumbersome with wide XOR gates and redundant column decoders.
Innovation Solution
The integration of multiplexer circuitry and syndrome generation circuitry with XOR logic gates in a logic tree architecture, combined with address converter circuitry and redundancy program circuits, enables efficient ECC and column redundancy operations, reducing latency and area/power consumption by sharing ECC circuitry between read and write paths and eliminating redundant column decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC techniques with wide XOR gates are used to improve data reliability, then error correction capability is enhanced, but circuit area and power consumption increase
Solution Approach 1:
The patent divides the memory array into multiple banks, each with its own ECC circuitry. This segmentation allows each bank to have smaller, more manageable XOR gates rather than one large XOR gate for the entire array, reducing the area requirement for each ECC unit while maintaining overall error correction capability.
Solution Approach 2:
The patent introduces a third dimension to ECC operation by implementing separate read-path and write-path ECC circuits that operate in different temporal dimensions. The write-path ECC generates check bits during write operations, while the read-path ECC verifies data during read operations, allowing area sharing between the two paths and reducing total circuit area.
2Reliability
If conventional ECC techniques with wide XOR gates are used to improve error correction capability, then reliability is enhanced, but power consumption increases
Solution Approach 1:
The patent implements periodic ECC operations where check bits are generated during write operations and verified during subsequent read operations. This periodic action allows the ECC circuitry to be active only when needed rather than continuously, reducing overall power consumption while maintaining error correction capability.
Solution Approach 2:
By separating ECC operations into read-path and write-path dimensions, the patent allows different portions of the ECC circuitry to be active at different times. The write-path XOR gates operate during writes while read-path XOR gates operate during reads, enabling area and power sharing between the two paths.
3Reliability
If redundant column decoders are implemented to improve manufacturing yield, then column redundancy capability is enhanced, but device complexity increases
Solution Approach 1:
The patent implements a universal column decoder that serves both normal operation and redundancy activation functions. The same decoder circuitry is used for addressing regular columns and for activating redundant columns when defects are detected, eliminating the need for separate redundant column decoders and reducing overall device complexity.
Solution Approach 2:
The patent merges the normal column selection function and the redundant column activation function into a single integrated column decoder. By combining these functions, the patent reduces the number of separate decoder circuits needed while maintaining the capability to access both normal and redundant columns, thereby reducing device complexity.
4Ease of operation
If redundant column decoders are added to simplify column redundancy management, then ease of operation is improved, but area requirements increase
Solution Approach 1:
The universal column decoder is designed to handle both normal column addressing and redundant column activation through a unified interface. This multi-functionality simplifies the operation of column redundancy management while avoiding the area overhead of separate decoder circuits, as the same hardware resources are reused for both functions.
Data Source
AI summary
An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.