Memory Array ECC Partitioning for Reflow-Induced Bit Errors
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces issues with data corruption during the manufacturing process of memory arrays, particularly due to the reflow process, which can damage memory cells and introduce errors in stored data.
Innovation Solution
Implementing a method that configures memory arrays with error correction codes (ECCs) such as Hamming, Reed-Solomon, or BCH codes, and parity checks to detect and correct errors introduced during the reflow process, by dividing the memory array into separate portions with different ECC configurations to provide enhanced error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes (ECCs) and parity checks are implemented in memory arrays, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory array is divided into multiple portions, with different ECC configurations applied to different segments. This allows error correction to be implemented selectively in regions most susceptible to reflow damage while maintaining simpler structures in less vulnerable areas, thus improving reliability without uniformly increasing complexity across the entire device.
Solution Approach 2:
Different portions of the memory array are configured with different ECC schemes tailored to their specific vulnerability profiles. The first portion through fourth portion each receive customized error correction configurations based on their location and susceptibility to manufacturing defects, optimizing the balance between reliability improvement and complexity management.
2Manufacturing precision
If memory arrays are divided into multiple portions with different ECC configurations, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The memory array is segmented into four distinct portions, each subjected to different ECC configurations during manufacturing. This segmentation enables targeted error correction strategies for each segment based on its specific manufacturing vulnerabilities, improving overall manufacturing precision while managing complexity through modular configuration.
Solution Approach 2:
Different ECC parameters and configurations are applied to different portions of the memory array. By varying the error correction parameters (such as ECC code type, parity check strength, and correction capability) across different segments, the system optimizes manufacturing precision for each region without requiring a uniformly complex structure throughout.
Data Source
AI summary
A method of screening weak bits in a memory array includes dividing the memory array into a first and a second memory array, storing a first set of data in the first memory array, performing a first baking process on the first memory array or applying a first magnetic field to the first memory array, determining that a first portion of the first set of data stored in the first memory array is altered by the first baking process or the first magnetic field, and at least one of replacing memory cells of a first set of memory cells that are storing the first portion of the first set of data with corresponding memory cells in the second memory array of the memory array, or not using the memory cells of the first set of memory cells storing the first portion of the first set of data.