Memory Array ECC Plane Access via Host Command
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Solution Overview
Problem
Existing memory devices face challenges in efficiently utilizing memory array space for error correction codes (ECC) and metadata storage, leading to suboptimal storage capacity and power consumption, as ECC functionality is often limited to on-die implementations that do not fully leverage the potential of memory arrays.
Innovation Solution
A memory device architecture that allows a host device to directly access a portion of the memory array reserved for ECC functions, enabling ECC data storage and retrieval without relying on on-die ECC circuits, and also uses this space for additional user data or metadata when ECC is disabled, by modifying access commands to differentiate between user data and ECC/data planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC circuits are implemented to provide error correction functionality, then data reliability is improved, but storage capacity and power consumption are worsened due to limited memory array utilization
Solution Approach 1:
The patent implements dynamic ECC functionality where the memory device can operate in different modes: with on-die ECC circuits enabled or disabled. The host device can selectively access ECC data planes when needed, allowing the system to adapt between high reliability mode (ECC enabled) and high capacity mode (ECC disabled), thus dynamically resolving the contradiction between reliability and storage capacity
Solution Approach 2:
The memory array is designed to serve multiple functions: it can store both user data and ECC data, and the same memory space can be used for different purposes depending on whether ECC is enabled. The host device can access the memory array for both data storage and ECC operations, making the system universal and able to handle both reliability-critical and capacity-critical scenarios
2Reliability
If on-die ECC circuits are implemented to ensure data integrity, then reliability is improved, but power consumption increases due to continuous ECC operations
Solution Approach 1:
Instead of continuous ECC operations, the patent implements periodic ECC checking where the host device selectively accesses ECC data planes only when error correction is needed. The memory device can switch between ECC-enabled mode (periodic checking) and ECC-disabled mode (no checking), reducing power consumption by performing ECC operations only periodically rather than continuously
Solution Approach 2:
The patent extracts the ECC functionality from being a mandatory continuous on-die operation and makes it an optional selective function. The host device can choose to access ECC data planes only when required, separating the ECC function from the basic memory operation and allowing power-saving modes where ECC is disabled entirely when not needed
3Reliability
If memory array space is reserved for ECC functions, then data reliability is improved, but storage capacity for user data is reduced
Solution Approach 1:
The patent implements dynamic allocation of memory array space where ECC data planes can be activated or deactivated based on system needs. When ECC is disabled, the entire memory array including previously reserved ECC space becomes available for user data, dynamically adjusting the balance between reliability and storage capacity
Solution Approach 2:
The memory array is designed with multi-functionality where the same physical space serves dual purposes: storing user data when ECC is disabled and storing ECC data when ECC is enabled. The host device can access the memory array for both purposes, making the storage space universal and eliminating the need for permanently dedicated ECC regions
4Quantity of substance
If host device directly accesses memory array for ECC data, then storage capacity is improved, but device complexity increases due to modified command protocols
Solution Approach 1:
The patent segments the memory array into distinct data planes and ECC planes, allowing the host device to selectively access different portions based on the operation type. The command protocol is segmented to include specific indicators for ECC operations versus standard memory operations, organizing the complexity into manageable segments rather than a monolithic complex system
Data Source
AI summary
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.