Memory Array ECC Architecture for Reflow-Induced Bit Errors
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces issues with data corruption during the reflow process in memory arrays, where solder paste is used to attach electrical components to contact pads, leading to bit errors in memory cells.
Innovation Solution
Implementing a method that configures a memory array with first and second error correction codes (ECCs) to correct bit errors introduced during the reflow process, where the first ECC provides N-bits of error correction and the second ECC provides additional M1-bits of protection, allowing for effective data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If solder paste is used to attach electrical components to contact pads during the reflow process, then electrical components are securely attached to the memory array, but bit errors are introduced in memory cells due to data corruption
Solution Approach 1:
The patent applies preliminary action by configuring error correction codes (ECCs) in the memory array before the reflow process occurs. The ECCs are pre-configured to detect and correct bit errors that may be introduced during the reflow process, thereby maintaining data integrity despite the harmful effects of the attachment process.
2Reliability
If error correction codes (ECCs) are configured in the memory array, then bit errors introduced during the reflow process are corrected, but the device complexity increases
Solution Approach 1:
The patent applies partial action by configuring ECCs selectively in specific portions of the memory array rather than throughout the entire array. This approach provides sufficient error correction capability to handle bit errors introduced during reflow while minimizing the increase in device complexity by limiting the ECC implementation to only where needed.
Data Source
AI summary
A method of correcting errors in a memory array. The method includes configuring a first memory array with a first error correction code (ECC) to provide error correction of data stored in the first memory array, configuring a second memory array with a second ECC to provide error correction of the data stored in the first memory array, performing a reflow process on the first and second memory array, and correcting data stored in the first memory array based on at least the first ECC or the second ECC. The first memory array includes a first set of memory cells arranged in rows and columns. The second memory array includes a second set of memory cells arranged in rows and columns.