Memory Array ECC Layout for Single-Pass SECDED Access

Solution Overview

Problem

Existing semiconductor memory devices face challenges in efficiently storing and accessing error correction information without impacting performance, particularly in architectures that require multiple passes to retrieve data and parity bits, leading to increased latency and power consumption.

Innovation Solution

A semiconductor memory device architecture that enables single-pass access of error correction code (ECC) information by storing ECC data in both data column planes and an extra column plane, allowing for single error correction and double error detection (SECDED) with reduced latency and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple passes are used to retrieve data and parity bits, then error correction capability is improved, but access latency increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidaccess latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The memory array is segmented into data column planes and an extra column plane, with specific columns designated for data storage and other columns for parity bit storage. This segmentation allows simultaneous access to both data and parity bits in a single pass, resolving the contradiction between error correction capability and access latency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an additional spatial dimension by adding an extra column plane alongside the data column planes. This dimensional expansion enables parallel storage and retrieval of both data and parity information, eliminating the need for multiple sequential access passes while maintaining SECDED capability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple passes are used to retrieve data and parity bits, then error correction capability is improved, but power consumption increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The memory array is segmented into data column planes and an extra column plane, with specific columns designated for data storage and other columns for parity bit storage. This segmentation allows simultaneous access to both data and parity bits in a single pass, resolving the contradiction between error correction capability and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent enables continuous single-pass access to both data and parity bits without interruption or additional access cycles. This continuous operation eliminates the energy expenditure associated with multiple sequential access passes, reducing overall power consumption while maintaining error correction capability.

Inventive Principle:

Principle #20Continuity of useful action

3Reliability

If ECC information is stored in the array with associated data, then error detection and correction capability is improved, but device complexity increases

Engineering Contradiction:

Improveerror detection and correction capabilityVSAvoidarchitecture complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The memory array is segmented into data column planes and an extra column plane, with specific columns designated for data storage and other columns for parity bit storage. This segmentation allows simultaneous access to both data and parity bits in a single pass, resolving the contradiction between error correction capability and access latency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The extra column plane serves multiple functions: storing parity bits for SECDED operations, providing additional storage capacity, and enabling flexible memory configurations. This multi-functionality reduces overall device complexity by consolidating multiple roles into a single structural element.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260051358A1Apparatuses and methods for configurable ECC modes

Publication Date: 2026.02.19 MICRON TECHNOLOGY INC

AI summary

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.