Memory Array Edge Cell Layout for Etch Variation Robustness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory array circuits face challenges in sustaining process variations caused by plasma etching or chemical mechanical polishing during fabrication, leading to under-etching or over-etching issues, which affect the yield and read/write performance of memory cells.
Innovation Solution
The implementation of a memory array circuit design that includes inner and edge memory cells with different physical dimensions and operation conditions, along with the use of dummy cells surrounding the array to provide a margin and prevent etching errors, enhancing the robustness and symmetry of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are fabricated using standard array design, then manufacturing process is simple, but process variations cause under-etching or over-etching leading to low yield
Solution Approach 1:
The patent applies local quality by creating different cell types (inner cells and edge cells) with different physical dimensions and characteristics. Edge cells are designed with different etch margins compared to inner cells, allowing each region of the array to be optimized for its specific fabrication challenges. This local differentiation enables the array to tolerate process variations that would otherwise cause uniform failures across the entire array.
Solution Approach 2:
The patent implements preliminary action by pre-compensating for etching variations through asymmetric cell design. Before fabrication, the edge cells are designed with larger etch margins to account for anticipated under-etching or over-etching. This proactive design approach allows the array to maintain functionality even when process variations occur during manufacturing, thereby improving yield without requiring complex real-time control.
2Reliability
If uniform memory cells are used throughout the array, then design is simple, but edge cells suffer from etching errors affecting read/write performance
Solution Approach 1:
The patent differentiates between inner cells and edge cells, assigning different physical characteristics to each. Edge cells are designed with larger dimensions and different etch margins to compensate for the heightened susceptibility to etching errors at array boundaries. This local quality approach ensures that cells in critical edge positions have the robustness needed to maintain read/write performance despite process variations.
Solution Approach 2:
The patent provides beforehand cushioning by incorporating extra etch margin into edge cell designs. This additional margin acts as a buffer that absorbs the impact of etching variations, preventing them from degrading cell functionality. The cushioning is built into the design phase, ensuring that even when etching deviates from specifications, edge cells maintain sufficient performance margins.
3Stability of the object's composition
If asymmetric cell design is implemented to compensate for etching variations, then process robustness improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes physical parameters of edge cells relative to inner cells, specifically increasing the dimensions and etch margins of edge cells. This parameter differentiation creates a design that is inherently more robust to etching variations. By adjusting these parameters during the design phase, the array achieves process robustness without requiring tighter control during manufacturing, effectively trading design complexity for manufacturing tolerance.
Data Source
AI summary
A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.