Semiconductor Memory Array Layout for Stable Edge-Cell Reading
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Solution Overview
Problem
The miniaturization of semiconductor devices with memory arrays is hindered by manufacturing variations causing significant resistance value changes in memory cells at the outer circumferential portions, leading to reading errors, especially in MRAMs, where the difference in resistance values is small and variations are large.
Innovation Solution
A semiconductor device design that includes a memory array with a central memory cell region surrounded by dummy cell regions, where dummy cells with the same configuration as memory cells are used to stabilize the characteristics, and additional dummy cells without storage elements are employed to supply a predetermined voltage to the source line during reading, effectively utilizing the dummy cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of the memory cell is shrunk for miniaturization, then the device size is reduced, but the characteristic change due to manufacturing variation of memory cells at the outer circumferential portion becomes large, leading to reading errors
Solution Approach 1:
The memory array is segmented into a central memory cell region and surrounding dummy cell regions. The dummy cell regions are further divided into first dummy cell regions containing dummy cells with storage elements and second dummy cell regions containing dummy cells without storage elements. This segmentation allows different zones to serve different functions in compensating for manufacturing variations and stabilizing reading operations.
Solution Approach 2:
Dummy cells act as intermediary elements between the central memory cell region and the outer circumferential boundary. These dummy cells compensate for manufacturing variations by providing a reference that stabilizes the characteristics of memory cells in the central region, thereby improving reading accuracy without requiring larger memory cell sizes.
2Reliability
If the number of memory cells in the dummy cell region is increased to reduce reading errors, then the reading accuracy is improved, but the area ratio of the dummy cell region increases, reducing the effective memory capacity
Solution Approach 1:
The first dummy cells in the first dummy cell regions serve multiple functions: they stabilize the characteristics of memory cells by compensating for manufacturing variations, and they can also be used as OTP (One Time Programmable) memory cells for storing trimming information. This multi-functionality reduces the need for separate trimming memory areas, thereby minimizing the overall dummy cell region area while maintaining reading accuracy.
Solution Approach 2:
Different types of dummy cells are strategically placed in different regions: the first dummy cell regions contain dummy cells with storage elements for OTP functionality and stability, while the second dummy cell regions contain dummy cells without storage elements for voltage supply. This localized differentiation optimizes the performance of each region while minimizing the total area required for dummy cells.
3Stability of the object's composition
If dummy cells without storage elements are added to supply predetermined voltage to the source line, then the reading operation stability is improved, but the number of unused memory cells increases
Solution Approach 1:
Dummy cells without storage elements are specifically placed in the second dummy cell regions where their primary function is to supply predetermined voltage to the source line during reading operations. This localized placement ensures voltage stability for reading operations while confining the unused cells to specific regions, allowing the rest of the memory array to maintain full functionality.
Solution Approach 2:
The dummy cells with storage elements in the first dummy cell regions are designed with the same configuration as the memory cells in the central region, allowing them to serve as copies that can be used for OTP functionality. This copying approach allows the system to utilize the dummy cell structure effectively without requiring additional unique components.
Data Source
AI summary
A semiconductor device includes a memory array. In a plan view, the memory array has a memory cell region arranged at a center portion and dummy cell regions arranged at an outer circumferential portion. In the dummy cell regions, a dummy cell connected to a word line is arranged, the dummy cell has a transistor whose gate terminal is connected to the word line and to whose drain terminal a ground voltage is supplied. At a time of performing a reading operation of the memory cell, the transistor is made in a conductive state so that the ground voltage is supplied to the source lines.