Memory Array Error Correction for Interleaved Read-Modify-Write
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Solution Overview
Problem
Existing memory devices face performance penalties due to the need for frequent refresh operations to prevent data corruption from leakage in DRAM, which consumes power and interrupts read/write operations, and current error correction schemes compromise operational speed and circuit real estate.
Innovation Solution
The solution involves dividing the column cycle into two halves, allowing for error correction and check bit regeneration during an interleaved portion of a different address cycle, enabling extended refresh times and reduced power consumption while maintaining performance by interleaving read, modify, and write operations with error correction code generation and masking at faster clock rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refresh operations are performed to prevent data corruption from leakage in DRAM, then data reliability is improved, but power consumption increases and read/write operations are interrupted
Solution Approach 1:
The column cycle is divided into two distinct halves: a first half dedicated to read operations and a second half dedicated to write operations. This segmentation allows refresh operations to be performed during the interleaved portion without interfering with either read or write operations, thereby maintaining data reliability while reducing power consumption interruptions
Solution Approach 2:
Error correction and check bit regeneration are performed in advance during the interleaved portion of the column cycle before the actual read/write operations begin. By completing error correction beforehand, the system ensures data reliability is maintained while avoiding power consumption spikes during critical data operations
2Reliability
If error correction schemes are implemented to enhance memory array data storage reliability, then data reliability is improved, but operational speed and circuit real estate are compromised
Solution Approach 1:
Error correction and check bit regeneration are performed periodically during the interleaved portion of the column cycle. This periodic execution ensures that error correction is completed before data operations begin, maintaining operational speed while ensuring data storage reliability through systematic error checking
Solution Approach 2:
The system maintains continuous operation by performing error correction during the interleaved portion without interrupting the main data flow. The column cycle continues uninterrupted with read operations in the first half and write operations in the second half, ensuring both speed and reliability
Data Source
AI summary
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.