Memory Array Error Logging Circuit for Targeted Off-Lining
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Solution Overview
Problem
Conventional memory systems inefficiently track error-prone memory cells, requiring hosts to manage complex address mappings and error information, leading to suboptimal off-lining strategies.
Innovation Solution
Incorporating an off-lining logging circuit within the memory device to identify error-prone regions by counting errors and generating candidate addresses for off-lining, allowing the host to efficiently manage memory array portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host tracks errors across different locations of the memory array to determine which memory cells to take off-line, then error tracking capability is improved, but device complexity and host overhead increase
Solution Approach 1:
The memory device performs error tracking and off-lining determination autonomously without requiring continuous host intervention. The device monitors its own error rates across different locations and independently identifies which memory cells should be taken off-line, thereby reducing host overhead while maintaining reliable error tracking capability.
Solution Approach 2:
The patent introduces an intermediary mechanism within the memory device that handles the complex error tracking and decision-making process. This intermediary structure enables the device to manage error information internally and present simplified results to the host, reducing the complexity burden on the host system.
2Adaptability or versatility
If the host manages mapping between logical and physical addresses in the array, then address management capability is improved, but device complexity increases
Solution Approach 1:
The memory device autonomously manages the mapping between logical and physical addresses by tracking which physical locations have high error rates and adjusting address assignments accordingly. The device performs this mapping management internally without requiring extensive host involvement, thereby maintaining adaptability while reducing complexity.
3Productivity
If the memory device generates information about which memory cells should be offlined, then off-lining efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory array into different locations or blocks and tracks error rates separately for each segment. This segmentation enables the device to generate targeted off-lining information for specific regions without requiring complex analysis of the entire memory array, thereby improving off-lining efficiency while managing circuit complexity through structured organization.
Data Source
AI summary
A memory device includes an off-lining logging circuit. The memory device detects errors in the memory array as well as one or more addresses which identify where in the array the error was located. The off-lining logging circuit counts errors in different portions of the array, such as sections and/or column planes, based on the addresses. If the count value crosses a threshold, the portion may be identified as a candidate for off-lining. In some examples, a host device may receive off-lining candidate address information from the memory and off-line the identified portions.