3D Memory Array Conductor Tier as Etch-Stop for Precise Patterning

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Solution Overview

Problem

Existing methods for forming memory arrays with strings of memory cells face challenges in accurately etching channel openings, TAV openings, and trenches to desired elevations, often requiring separate etch-stop structures which increase costs and complexity.

Innovation Solution

The use of metal material as an etch-stop during the etching process for forming channel openings, TAV openings, and trenches, eliminating the need for separate etch-stop structures and simplifying the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate etch-stop structures are used to control etching depth, then etching precision is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveetching depth controlVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the etch-stop function with the existing conductor tier structure. The conductor tier serves dual purposes: as an electrical conductor and as an etch-stop layer. This eliminates the need for separate etch-stop structures while maintaining precise etching depth control, directly resolving the contradiction between etching precision and device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductor tier is given multiple functions: it acts as both an electrical conductor for memory cell operation and as an etch-stop structure for controlling etching depth. This multi-functionality approach eliminates redundant structures and simplifies the overall device architecture while maintaining manufacturing precision

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If separate etch-stop structures are used, then etching control is improved, but manufacturing cost increases

Engineering Contradiction:
Improveetching depth controlVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

By combining the etch-stop function with the existing conductor tier, the patent eliminates the need for additional materials and processing steps. This reduces manufacturing cost while maintaining precise etching depth control, directly addressing the contradiction between manufacturing precision and ease of manufacture

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The conductor tier serves itself by performing both its electrical conduction function and its etch-stop function. This self-service approach eliminates the need for separate dedicated etch-stop structures, reducing material costs and simplifying the manufacturing process

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If metal material is used as etch-stop, then fabrication process is simplified, but etching precision control may be affected

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidetching precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent utilizes the specific physical and chemical parameters of metal materials (such as etching rate, selectivity, and resistance to common etchants) to achieve precise etching depth control. By carefully selecting metal materials with appropriate etching characteristics, the patent maintains etching precision while simplifying the fabrication process

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12315813B2Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
Publication Date: 2025.05.27 MICRON TECHNOLOGY INC
  • US12315813B2 patent drawing
  • US12315813B2 patent drawing
  • US12315813B2 patent drawing

AI summary

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAV constructions that individually extend through a lowest of the conductive tiers. The TAV constructions individually comprise an insulative lining having a lowest surface that is directly against metal material in the lowest conductive tier. Other embodiments, including method, are disclosed.