3D Memory Array Stack With Silicon Nitride Etch-Stop Tiers
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Solution Overview
Problem
Current methods for forming memory arrays, such as NAND architecture, face challenges in efficiently creating vertically-stacked memory cells and ensuring reliable electrical access through the use of stair-step structures and sacrificial materials.
Innovation Solution
The proposed method involves forming a memory array with strings of memory cells using a 'gate-last' or 'replacement-gate' processing approach, which includes forming vertically-alternating tiers of conductive and insulative materials, etching channel openings, and removing sacrificial material to create channel-material strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cells are formed using conventional methods, then memory density is increased, but manufacturing complexity and reliability issues arise due to stair-step structures and sacrificial materials
Solution Approach 1:
The patent removes the stair-step structure and sacrificial materials from the conventional vertically-stacked memory cell formation process. By extracting these complex components, the invention simplifies the manufacturing process while maintaining the three-dimensional stacked architecture that provides high memory density.
Solution Approach 2:
Instead of forming memory cells in a conventional planar arrangement and then stacking them with complex interconnect structures, the patent inverts the approach by directly forming vertically-stacked memory cells in a simplified configuration, eliminating the need for stair-step structures and sacrificial materials.
2Quantity of substance
If vertically-stacked memory cells are formed using conventional methods, then memory density is increased, but electrical access reliability deteriorates due to complex interconnect structures
Solution Approach 1:
The patent extracts and eliminates the complex stair-step interconnect structures from the vertically-stacked memory cell design. This removal of unnecessary interconnect complexity directly improves electrical access reliability while preserving the high-density three-dimensional architecture.
3Ease of manufacture
If gate-last or replacement-gate processing is used, then manufacturing simplicity is improved, but process precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-forming the gate structure before completing the memory cell formation process. This gate-last or replacement-gate approach allows the gate to be formed in advance, simplifying the overall manufacturing process while requiring precise control during the subsequent steps to ensure proper alignment and integration.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.