Memory Array Imminent Read Failure Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems, especially in safety-critical applications like automotive systems, face challenges in predicting uncorrectable read failures in non-volatile memory (NVM) before they become catastrophic, as existing error correcting code (ECC) techniques can only correct single-bit errors and may not accurately indicate imminent read failures.
Innovation Solution
The implementation of a threshold voltage technique that combines ECC with a margin read, using a circuit with an address sequencer, ECC circuit, and threshold voltage level adjuster to detect imminent read failures by performing reads at margin threshold voltage levels, and tracking ECC correction counts to identify increasing errors over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC is used to correct single-bit errors, then error correction capability is improved, but the ability to detect imminent read failures deteriorates
Solution Approach 1:
The patent performs preliminary actions by conducting reads at margin threshold voltage levels before actual read failures occur. The system tracks ECC correction counts over time and identifies trends that indicate imminent failures, allowing preventive action before catastrophic failures happen. This is achieved through the threshold voltage level adjuster that performs reads at multiple voltage levels and the counter that tracks correction counts across multiple reads.
2Measurement precision
If margin reads are performed at threshold voltage levels, then imminent read failure detection is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by having the threshold voltage level adjuster serve multiple purposes: it performs reads at normal voltage levels for regular data access, performs reads at margin threshold voltage levels for failure detection, and works cooperatively with the ECC circuit for error correction. The same hardware infrastructure handles both normal operation and diagnostic functions, reducing the need for separate dedicated circuits.
Solution Approach 2:
The system performs self-diagnosis through the margin reads and ECC correction tracking. The memory system automatically monitors its own health by counting ECC corrections over time and detecting trends that indicate degradation, without requiring external diagnostic equipment. The counter and threshold voltage level adjuster enable the system to self-monitor and self-diagnose impending failures.
3Measurement precision
If ECC correction count tracking is implemented, then failure prediction accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements feedback by continuously tracking ECC correction counts and using this information to predict future failures. The counter stores correction counts from multiple reads, and the system analyzes trends in this feedback data to determine when a read failure is imminent. This feedback mechanism allows the system to learn from past errors and predict future failures based on the rate of correction accumulation.
Data Source
AI summary
A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.