Memory Array Fast Zero Mode Sequential Write

Solution Overview

Problem

Existing memory devices face challenges in efficiently accessing and writing zeros to large sections of memory arrays without requiring additional hardware, which increases cost and size, particularly in modes of operation like Fast Zero mode where sequential access is necessary.

Innovation Solution

The implementation of a Fast Zero mode that utilizes internal address counters to sequentially access and write zeros to memory cells within a memory array, sharing counters with other modes to minimize hardware requirements, and employing a command controller to generate internal addresses for sequential access, allowing for faster zero writing without relying on the input/output interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If additional hardware components are added to enable sequential access to memory cells, then access functionality is improved, but device cost and size increase

Engineering Contradiction:

Improvesequential access capabilityVSAvoidhardware components

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent makes existing address counters serve dual purposes: they continue to generate addresses for normal memory operations while simultaneously enabling sequential access to all memory cells in Fast Zero mode. This multi-functionality eliminates the need for separate dedicated hardware for sequential access, resolving the contradiction between improved operation capability and device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The existing address counters within the memory device are utilized to perform the sequential access function without requiring external or additional counting hardware. The counters essentially serve themselves by being repurposed for Fast Zero mode operations, eliminating the need for extra hardware components while maintaining sequential access capability.

Inventive Principle:

Principle #25Self-service

2Ease of operation

If additional hardware components are added to enable sequential access to memory cells, then access functionality is improved, but device size increases

Engineering Contradiction:

Improvesequential access capabilityVSAvoiddevice size

Core Design Contradiction:

Ease of operationVSArea of stationary object

Solution Approach 1:

The patent makes existing address counters serve dual purposes: they continue to generate addresses for normal memory operations while simultaneously enabling sequential access to all memory cells in Fast Zero mode. This multi-functionality eliminates the need for separate dedicated hardware for sequential access, resolving the contradiction between improved operation capability and device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The existing address counters within the memory device are utilized to perform the sequential access function without requiring external or additional counting hardware. The counters essentially serve themselves by being repurposed for Fast Zero mode operations, eliminating the need for extra hardware components while maintaining sequential access capability.

Inventive Principle:

Principle #25Self-service

3Reliability

If traditional write methods are used to write zeros to memory array, then I/O interface is utilized, but writing speed is reduced

Engineering Contradiction:

Improvewrite operationVSAvoidwriting speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the address generation function from the I/O interface path and places it directly within the memory device using internal address counters. By taking out the address sequencing capability from the external interface and embedding it internally, the system can write zeros directly to memory cells without waiting for external address signals, thereby dramatically improving writing speed while maintaining write operation reliability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The internal address counters are pre-configured and ready to generate sequential addresses before the Fast Zero write operation begins. This preliminary preparation of address sequences allows the write operation to proceed at maximum speed without address generation delays, improving productivity while ensuring reliable write operations.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11132142B2Systems and methods for writing zeros to a memory array

Publication Date: 2021.09.28 MICRON TECHNOLOGY INC

AI summary

A memory device may include a first wordline and a second wordline, each having multiple memory cells. The memory device may also include control circuitry to facilitate writing a data pattern to the memory cells of the first wordline and facilitate copying the data pattern from the first wordline to the second wordline. Copying the first wordline to the second wordline may include activating the second wordline such that the first wordline and the second wordline are simultaneously active. A memory cell of the first wordline may be written a data value of the data pattern, and the memory cell may drive, at least partially, a corresponding memory cell of the second wordline with the data value.