Memory Array Fault Detection Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory technologies, such as DDR5 SDRAM, lack the capability for fault detection during data storage, leading to potential data loss due to the inability to verify the storage function of memory cells.
Innovation Solution
A detection circuit is introduced, comprising a generation unit that generates random detection data, a first drive unit that transmits this data to the memory array, and a comparison unit that compares the stored data with the original random detection data to determine if the storage function is functioning correctly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a detection circuit is introduced to enable fault detection on the storage function of the memory array, then the reliability of data storage is improved, but the device complexity increases due to the additional generation unit, first drive unit, and comparison unit
Solution Approach 1:
The generation unit generates random detection data in advance before the memory array performs normal data storage operations. This preliminary action allows the detection circuit to verify storage function proactively, enabling fault detection before actual data loss occurs, thus improving reliability without requiring complex real-time monitoring during normal operations
2Measurement precision
If random detection data is generated and transmitted to the memory array for storage verification, then the measurement precision of storage function is improved, but the loss of time increases due to the additional detection process
Solution Approach 1:
The detection circuit performs storage function verification periodically using random detection data, rather than continuously monitoring every data operation. This periodic action provides sufficient measurement precision to detect storage faults while minimizing time loss by allowing normal memory operations to proceed between detection cycles
Data Source
AI summary
The present disclosure provides a detection circuit, including: a generation unit provided with a plurality of output terminals and configured to generate random detection data and output one bit of the random detection data through each output terminal; a first drive unit provided with a plurality of first input terminals connected to the plurality of output terminals of the generation unit in one-to-one correspondence and a plurality of output terminals connected to a memory array, and configured to transmit the random detection data to the memory array, wherein the memory array is configured to store the random detection data; and a comparison unit provided with a plurality of first input terminals connected to the plurality of output terminals of the generation unit in one-to-one correspondence and a plurality of second input terminals connected to the memory array.