3D Memory Array Tiers for Stable Ferroelectric Polarization
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Solution Overview
Problem
Existing memory technologies face challenges in maintaining the polarization state of ferroelectric materials used in memory cells, particularly in non-volatile capacitors and transistors, as reading the memory state can reverse the polarization, requiring immediate rewriting of the cell.
Innovation Solution
A memory array structure comprising vertically-alternating tiers of insulative material and memory cells, where each memory cell includes a transistor and a capacitor with a ferroelectric gate insulator and capacitor insulator, allowing for stable polarization states without reversing during read operations by using silicon nitride or silicon dioxide as insulative materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ferroelectric material is used in memory cells for non-volatile storage, then data retention is improved, but polarization reversal during read operations occurs causing data integrity issues
Solution Approach 1:
The memory array is divided into multiple tiers with alternating insulative and memory cell layers. This segmentation allows independent control and reading of different memory cell tiers, enabling read operations on one tier without affecting the polarization state of ferroelectric materials in other tiers.
Solution Approach 2:
Different tiers of memory cells use different insulative materials (e.g., silicon nitride in some tiers, silicon dioxide in others) with varying dielectric properties. This local differentiation in material quality allows optimization of each tier's electrical characteristics to prevent polarization reversal during read operations while maintaining non-volatile storage capabilities.
2Stability of the object's composition
If vertically-alternating tiers of insulative material and memory cells are implemented, then polarization stability is improved, but device complexity increases
Solution Approach 1:
The vertically-alternating tier structure serves multiple functions simultaneously: it provides electrical isolation between memory cell tiers, enables independent read/write operations on different tiers, stabilizes polarization states through controlled dielectric environments, and facilitates scalable memory array expansion. This multi-functionality justifies the increased structural complexity.
Solution Approach 2:
The patent transitions from planar memory cell arrangements to a vertical three-dimensional architecture with alternating tiers. This dimensional change allows multiple memory cell tiers to be stacked vertically, improving polarization stability through controlled electrical environments in each tier while enabling higher storage density despite increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enables non-volatile memory storage with stable polarization states, preventing polarization reversal during read operations, thus maintaining data integrity without the need for immediate rewriting.
Implementation Method 1
at least a portion of the gate insulator comprises ferroelectric material
Implementation Method 2
Energy as an electric field may be electrostatically stored within such material
Implementation Method 3
A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material
Implementation Method 4
using silicon nitride or silicon dioxide as insulative materials
Data Source
AI summary
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.