3D Memory Array Filling Structure for Edge Transistor Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Transistors at the edge of memory arrays in 3D memory structures are prone to performance degradation due to differences in structure density during the preparation process, leading to defects like high off-state currents.
Innovation Solution
Incorporating a filling structure between adjacent memory arrays to equalize structure density, using virtual transistors that do not interfere with functional transistors, and employing insulating materials to provide mechanical support and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory arrays are stacked in 3D structure to increase storage density, then storage capacity is improved, but transistors at edge regions are prone to performance degradation due to structure density differences
Solution Approach 1:
The patent applies local quality by introducing filling structures specifically at edge regions where structure density differs from the isolation region. These filling structures locally increase the structure density at edge positions, making the structure density more uniform across different regions. This local modification prevents process defects and transistor performance degradation without affecting the overall 3D stacked architecture and storage density.
2Reliability
If filling structures are added between memory arrays to equalize structure density, then transistor performance is improved, but device complexity increases
Solution Approach 1:
The filling structures are designed to copy the same pattern and configuration in each isolation region between memory arrays. By using identical filling structure designs across all edge regions, the patent simplifies the manufacturing process and reduces overall device complexity despite adding multiple structures. The repetitive nature of the filling structures allows for standardized fabrication processes.
3Productivity
If virtual transistors are used as filling structures to simplify preparation process, then manufacturing efficiency is improved, but interference with functional transistors must be prevented
Solution Approach 1:
The patent extracts only the essential structural components needed for the filling function, creating simplified virtual transistor structures that lack the control gate element. By removing the control gate, these filling structures cannot function as active transistors and thus cannot interfere with functional transistors, while still providing the necessary structural support and density equalization. This extraction approach simplifies the preparation process while preventing harmful interference.
Data Source
Figure 1~2
Figure 3a~3b
Figure 4~5
AI summary
This application discloses a memory and a preparation method thereof, and an electronic device, and relates to the field of semiconductor storage technologies. The memory includes a substrate, a plurality of memory arrays, a filling structure, and an isolation spacer. The memory array includes a plurality of memory cells, the memory cells include a transistor and at least one capacitor that are stacked, and the at least one capacitor is electrically connected to a side that is of the transistor and that is away from the substrate. In a direction parallel to the substrate, the filling structure is located between transistors of two adjacent memory arrays. The isolation spacer is located on a side that is of the filling structure and that is away from the substrate, and in the direction parallel to the substrate, located between capacitors of the two adjacent memory arrays. The filling structure is disposed to increase structure density of a region between adjacent memory arrays. In this way, during a preparation process, a process defect of a film layer structure in an edge region of the memory array can be mitigated, thereby mitigating a performance degradation phenomenon of a transistor in the edge region of the memory array.