3D Memory Array Conductor Tier Layout for Precise Gate-Last Etching
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Solution Overview
Problem
Existing memory array fabrication methods face challenges in forming vertically-stacked memory cells with precise control over the formation of conductive and insulative layers, leading to potential etching issues and material loss, which can affect the integrity and performance of the memory cells.
Innovation Solution
A method involving 'gate-last' processing is employed, where horizontally-elongated lines of different composition are formed in the conductor tier, followed by the creation of vertically-alternating insulative and conductive tiers, with channel material strings extending through these tiers, and conductive material is used to electrically couple the channel material with the conductor tier, ensuring precise alignment and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form vertically-stacked memory cells, then the manufacturing process is simpler, but etching issues and material loss occur affecting cell integrity
Solution Approach 1:
The patent applies preliminary action by forming a mandrel structure before depositing the conductor tier and insulative tiers. The mandrel serves as a pre-established template that guides subsequent etching and material deposition, ensuring precise formation of channel material strings and preventing material loss during fabrication. This preliminary structure enables controlled material placement and maintains etching precision throughout the vertically-stacked memory cell formation process.
2Loss of substance
If precise control over conductive and insulative layers is implemented, then material loss is reduced, but the fabrication process becomes more complex
Solution Approach 1:
The patent implements the nested doll principle by creating a hierarchical structure where the conductor tier is nested within the insulative tiers, which are in turn nested within the mandrel structure. This nested arrangement of conductor tier, insulative tiers, and mandrel enables precise material placement and minimizes material loss during etching and deposition processes. Each nested layer protects and guides the formation of inner layers, reducing unwanted material removal while maintaining fabrication control.
3Manufacturing precision
If horizontally-elongated lines of different composition are formed in the conductor tier, then alignment precision is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies local quality by forming horizontally-elongated lines of different composition within the conductor tier at specific locations where precise alignment is required. These compositionally-different lines serve as local alignment features that guide subsequent processing steps without requiring the entire conductor tier to have complex multi-material construction. This localized approach to material differentiation achieves alignment precision while maintaining relative fabrication simplicity.
Data Source
AI summary
A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.