Memory Array Gate Structure Formation
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Solution Overview
Problem
Current memory array technologies face challenges in efficiently forming vertically-stacked memory cells with reliable gate structures and electrical connectivity, particularly in the 'gate-last' or 'replacement-gate' processing methods, which affect the retention and accessibility of data in non-volatile memory cells.
Innovation Solution
The method involves forming a stack with alternating conductive and insulative tiers, where the lower portion includes a sacrificial material layer between polysilicon-comprising layers, and specific intermediate layers with compositions like SiNx, SiNy bilayers, and carbon-doped SiNz, allowing for the formation of channel-material strings and conductive lines that electrically couple with the conductor tier, enabling effective data storage and access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-last or replacement-gate processing methods are used to form vertically-stacked memory cells, then manufacturing flexibility and device performance are improved, but process complexity and difficulty in achieving reliable gate structures increase
Solution Approach 1:
The patent forms intermediate layers (such as SiNx, SiNy bilayers, and carbon-doped SiNz) and sacrificial material layers before forming the final gate structure. These preliminary layers are prepared with specific compositions and thicknesses to enable subsequent gate formation processes to proceed reliably, reducing the complexity of the overall process while ensuring gate structure integrity.
Solution Approach 2:
The patent introduces intermediate layers with specific material compositions (SiNx, SiNy, carbon-doped SiNz) that act as mediators between the substrate and the final gate structure. These intermediate layers facilitate the formation of reliable gate structures by providing appropriate electrical, mechanical, and chemical properties that bridge the requirements of different processing stages.
2Quantity of substance
If vertically-stacked memory cells are formed with complex tiered structures, then memory density and storage capacity are improved, but manufacturing precision requirements and process difficulty increase
Solution Approach 1:
The patent divides the memory structure into multiple discrete tiers with alternating conductive and insulative layers. Each tier is formed as a separate unit with specific material compositions, allowing for modular fabrication and reducing the precision requirements for the overall structure by breaking down the complex formation process into manageable segments.
Solution Approach 2:
The patent employs intermediate layers with varying material parameters (composition, thickness, electrical properties) to control the formation of each tier. By adjusting parameters such as nitrogen content in SiNx/SiNy layers and carbon doping in SiNz layers, the patent optimizes each tier's properties to achieve high memory capacity while maintaining manufacturable precision levels.
3Adaptability or versatility
If sacrificial material layers are used in gate-last processing, then gate structure formation flexibility is improved, but additional process steps and time are required
Solution Approach 1:
The patent uses sacrificial material layers that are temporarily introduced to enable gate structure formation and are subsequently removed (taken out) after serving their purpose. This approach provides flexibility in gate formation by allowing the gate to be formed last, but the sacrificial layers are efficiently removed through selective etching processes to minimize additional processing time.
Solution Approach 2:
The sacrificial material layers are discarded after fulfilling their temporary function of enabling gate formation. The removal process is optimized to recover processing efficiency by using selective etching that quickly removes the sacrificial material without affecting the surrounding structures, thereby minimizing the time penalty associated with using sacrificial layers.
Data Source
AI summary
Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the upper and lower polysilicon-comprising layers. An upper intermediate layer is vertically between the upper polysilicon-comprising layer and the intervening-material layer. A lower intermediate layer is vertically between the lower polysilicon-comprising layer and the intervening-material layer. The lower intermediate layer and the upper intermediate layer comprise at least one of (a), (b), and (c), where (a): SiNx, where “x” is greater than 1.33 and no more than 2.0, or alternately where “x” is 0.5 to less than 1.33; (b): a bilayer comprising SiNy and comprising silicon dioxide positioned vertically relative one another, where “y” is 0.5 to no more than 2.0, the silicon dioxide of the bilayer being closer to the sacrificial material of the lowest first tier than is the SiNy; and (c): carbon-doped SiNz having carbon present at 0.1 to 10.0 atomic percent, “z” being 0.5 to no more than 2.0. Methods are disclosed.