Non-volatile Memory Array With Grouped Control Lines
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Solution Overview
Problem
Conventional EEPROMs face issues with leakage current due to defects in the tunneling oxide layer and suffer from program disturb and erase disturb phenomena, which affect the reliability and integration of non-volatile memory arrays.
Innovation Solution
A non-volatile memory array design featuring a charge storage structure with a silicon nitride layer, grouped control lines to prevent disturb phenomena, and a select transistor configuration that isolates unselected memory units during programming and erasing operations, ensuring reliable data storage and reduced fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a double layer gate structure with polysilicon floating gate is used, then non-volatile memory functionality is achieved, but integration with CMOS logic process becomes difficult and fabrication cost increases
Solution Approach 1:
The patent changes the material parameter of the gate structure from polysilicon floating gate to charge trapping material (silicon nitride), enabling the memory to function without requiring complex double layer gate structures while maintaining compatibility with standard CMOS logic processes
Solution Approach 2:
The patent replaces the expensive and complex polysilicon floating gate structure with a simpler, more cost-effective charge trapping material structure that can be integrated into standard CMOS processes, reducing fabrication costs while maintaining memory functionality
2Ease of operation
If electrons are uniformly distributed in the polysilicon floating gate layer, then programming is achieved, but leakage current increases due to sensitivity to tunneling oxide layer defects
Solution Approach 1:
The patent changes the charge storage mechanism from uniform electron distribution in polysilicon to localized electron trapping in silicon nitride defect states, which concentrates charges in specific regions and reduces sensitivity to tunneling oxide defects, thereby lowering leakage current
Solution Approach 2:
The charge trapping material acts as an intermediary between the tunneling oxide layer and the control gate, localizing charges in a way that prevents direct interaction with oxide defects and reduces leakage current while maintaining programming capability
3Ease of operation
If all bit lines in the same row are connected together, then programming operation is simplified, but program disturb and erase disturb occur in unselected memory units
Solution Approach 1:
The patent segments the bit line connections by introducing isolation transistors that control which memory units are connected to which bit lines, allowing selective connection during different operations to prevent disturb in unselected units while maintaining ease of operation for selected units
Solution Approach 2:
The patent introduces dynamic control of bit line connections through isolation transistors that can be turned on or off based on the operation being performed, enabling flexible connection configurations that prevent program disturb and erase disturb while maintaining operational simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design significantly reduces program disturb and erase disturb, enhances memory unit reliability, and simplifies the programming and reading processes while maintaining cost-effectiveness by using a silicon nitride charge storage layer and grouping control lines to prevent interference between memory units.
Implementation Method 1
Since the silicon nitride has capable of trapping electrons, the electrons injected into the silicon nitride layer just concentrate in local region
Implementation Method 2
When performing erasing operation by Fowler-Nordheim (FN) tunneling effect
Implementation Method 3
When performing programming operation by channel hot carrier injection
Data Source
AI summary
A non-volatile memory array including a plurality of memory units is provided. Each memory unit is serially connected with a select transistor and a memory cell. A source region is next to the select transistor while a drain region is next to the memory cell. The drain lines are arranged in parallel in column direction and connected with the drain regions of the memory units in one column. The bit lines are arranged in parallel in row direction and connected with the source regions of the memory units in one row. The word lines are arranged in parallel in column direction and connected with the select gates of the memory units in one column. The control lines are arranged in parallel in column direction and connected with the control gates of the memory units in one column. The control lines are grouped by two and electrically connected with each other.